摘要:
A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units. A pull-up device may be provided on the serial communication link to maintain a high voltage level on the link when it is not being driven by one of the bus interface units. The north bridge and south bridge may alternate between sending and receiving commands across the
摘要:
An advanced configuration and power interface operating system transparent method to control the wake-to-sleep and sleep-to-wake transitions includes: detecting a sleep enable command; temporarily blocking completion of the sleep enable command; generating an interrupt; configuring an input-output device; and completing the sleep enable command. The sleep enable command can be a write command to an advanced configuration and power interface sleep enable data storage unit. The generated interrupt can be a system management interrupt that invokes a basic input-output device configuration program.