摘要:
An advanced configuration and power interface operating system transparent method to control the wake-to-sleep and sleep-to-wake transitions includes: detecting a sleep enable command; temporarily blocking completion of the sleep enable command; generating an interrupt; configuring an input-output device; and completing the sleep enable command. The sleep enable command can be a write command to an advanced configuration and power interface sleep enable data storage unit. The generated interrupt can be a system management interrupt that invokes a basic input-output device configuration program.
摘要:
Example embodiments disclosed herein relate to implementing a power down state in a computing device. A sleep command is issued to place a computing device in a sleep state in response to receipt of a power off command at the computing device. Content of memory of the computing device is written to non-volatile storage of the computing device and the computing device is placed in a power off state.
摘要:
Systems and methods of determining a trust level from system management mode are disclosed. One such method includes: responsive to a system management mode interrupt (SMI), determining a trust level associated with code invoking the SMI; and responsive to determining that the trust level is untrusted, granting or denying a request made by the code invoking the SMI based at least in part on a type of the request.
摘要:
Systems and methods of determining a trust level from system management mode are disclosed. One such method includes: responsive to a system management mode interrupt (SMI), determining a trust level associated with code invoking the SMI; and responsive to determining that the trust level is untrusted, granting or denying a request made by the code invoking the SMI based at least in part on a type of the request.
摘要:
A computer system is provided, the computer system having a processor and a system memory coupled to the processor. The computer system also includes a Basic Input/Output System (BIOS) in communication with the processor. The BIOS selectively scrubs the system memory during a shutdown process of the computer system.
摘要:
A method to configure a device for remote management that is transparent to an advanced configuration and power interface (ACPI) operating system is described. The method includes configuring a device in a computer system when a transition between power states is being effected by the advanced configuration and power interface operating system including the step of causing the computer system to enter a non-ACPI mode in response to the transition being effected, configuring the device while in the non-ACPI mode, and completing the transition after the configuring of the device. The method may be stored in any media that is readable and executable by a computer system.
摘要:
A first controller can provide system state information and a second controller can receive the system state information. The second controller can be programmed to control the state of a component. The state of the component can be based on information programmed in the second controller and the system state information. The component can include an off state and an operating state indicated by a signal from the second controller.
摘要:
A method and system of executing stack-based memory reference code. At least some of the illustrated embodiments are methods comprising waking a computer system from a reduced power operational state in which a memory controller loses at least some configuration information, executing memory reference code that utilizes a stack (wherein the memory reference code configures the main memory controller), and passing control of the computer system to an operating system. The time between executing a first instruction after waking the computer system and passing control to the operating system takes less than 200 milliseconds.
摘要:
Systems and methods of securely updating BIOS are disclosed. One such system comprises a reprogrammable memory, a first and a second register, and comparison logic. The reprogrammable memory comprises a first portion and a protect input. The protect input is configured to disallow writes to at least the first portion when the memory protect input is at a first levels, and to allow writes to at least the first portion when the protect input is at a second level. The comparison logic is configured to drive a comparison output to a third level responsive to the first and second registers having equal values, and to drive the comparison output to a fourth level responsive to the first and second registers having different values. The comparison output is electrically coupled to the memory protect input.
摘要:
Systems, methodologies, media, and other embodiments associated with simulating a processor performance state by controlling a thermal management signal are described. One exemplary system embodiment includes a data structure for storing bit patterns that facilitate controlling a GPIO (General Purpose Input Output) block and addresses of locations to which the bit patterns can be written. The example system may also include a logic configured to receive a request to produce a performance state in a processor and to cause a frequency and voltage to be established in the processor in response to a thermal management signal being generated in response to writing the bit pattern(s) to the address(es).