HARDWARE MULTI-THREADING CO-SCHEDULING FOR PARALLEL PROCESSING SYSTEMS
    1.
    发明申请
    HARDWARE MULTI-THREADING CO-SCHEDULING FOR PARALLEL PROCESSING SYSTEMS 有权
    用于并行处理系统的硬件多线程协调调度

    公开(公告)号:US20110093638A1

    公开(公告)日:2011-04-21

    申请号:US12581694

    申请日:2009-10-19

    摘要: A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.

    摘要翻译: 提供了一种方法,信息处理系统和计算机程序产品,用于管理并行处理系统中的应用程序的操作系统干扰。 确定硬件多线程线程到至少一个处理核心的映射,并确定至少一个处理核心的第一和第二组逻辑处理器。 第一组包括至少一个处理核心的逻辑处理器中的至少一个,并且第二组包括至少一个处理核心的逻辑处理器的剩余部分中的至少一个。 处理器仅在至少一个处理核心的第一组逻辑处理器的逻辑处理器上调度应用程序任务。 仅在至少一个处理核心的第二组逻辑处理器的逻辑处理器上调度操作系统干扰事件。

    Hardware multi-threading co-scheduling for parallel processing systems
    2.
    发明授权
    Hardware multi-threading co-scheduling for parallel processing systems 有权
    并行处理系统的硬件多线程协同调度

    公开(公告)号:US08484648B2

    公开(公告)日:2013-07-09

    申请号:US12581694

    申请日:2009-10-19

    IPC分类号: G06F9/46 G06F13/24

    摘要: A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.

    摘要翻译: 提供了一种方法,信息处理系统和计算机程序产品,用于管理并行处理系统中的应用程序的操作系统干扰。 确定硬件多线程线程到至少一个处理核心的映射,并确定至少一个处理核心的第一和第二组逻辑处理器。 第一组包括至少一个处理核心的逻辑处理器中的至少一个,并且第二组包括至少一个处理核心的逻辑处理器的剩余部分中的至少一个。 处理器仅在至少一个处理核心的第一组逻辑处理器的逻辑处理器上调度应用程序任务。 仅在至少一个处理核心的第二组逻辑处理器的逻辑处理器上调度操作系统干扰事件。