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公开(公告)号：US07757069B2
公开(公告)日：2010-07-13
申请号：US11395777
申请日：2006-03-31
申请人： Brian F. Veale , John K. Antonio , Monte P. Tull
发明人： Brian F. Veale , John K. Antonio , Monte P. Tull
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F9/3897 , G06F15/7867
摘要： A reconfigurable processor including a plurality of reconfigurable execution units, a memory, an instruction queue, a configuration selection unit, and a configuration loader. The memory stores a plurality of steering vector processing hardware configurations for configuring the reconfigurable execution units. The instruction queue stores a plurality of instructions to be executed by at least one of the reconfigurable execution units. The configuration selection unit analyzes the instructions stored in the instruction queue and chooses one of the steering vector processing hardware configurations. The configuration loader determines whether one of the reconfigurable slots is available and reconfigures at least one of the reconfigurable slots with at least a part of the chosen steering vector processing hardware configuration responsive to at least one of the reconfigurable slots being available.
摘要翻译： 一种可重构处理器，包括多个可重构执行单元，存储器，指令队列，配置选择单元和配置加载器。 存储器存储用于配置可重配置执行单元的多个导向向量处理硬件配置。 指令队列存储要由可重新配置的执行单元中的至少一个执行的多个指令。 配置选择单元分析存储在指令队列中的指令，并选择导向矢量处理硬件配置之一。 所述配置加载器确定所述可重新配置的时隙之一是否可用，并且至少一个所述可重配置时隙具有所选择的导向向量处理硬件配置的至少一部分，以响应于所述可重配置时隙中的至少一个是可用的。
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2.发明申请公开(公告)号：US20110093638A1
公开(公告)日：2011-04-21
申请号：US12581694
申请日：2009-10-19
CPC分类号： G06F9/542 , G06F9/3851 , G06F9/3885 , G06F9/4812 , G06F9/4818
摘要： A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.
摘要翻译： 提供了一种方法，信息处理系统和计算机程序产品，用于管理并行处理系统中的应用程序的操作系统干扰。 确定硬件多线程线程到至少一个处理核心的映射，并确定至少一个处理核心的第一和第二组逻辑处理器。 第一组包括至少一个处理核心的逻辑处理器中的至少一个，并且第二组包括至少一个处理核心的逻辑处理器的剩余部分中的至少一个。 处理器仅在至少一个处理核心的第一组逻辑处理器的逻辑处理器上调度应用程序任务。 仅在至少一个处理核心的第二组逻辑处理器的逻辑处理器上调度操作系统干扰事件。
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公开(公告)号：US08484648B2
公开(公告)日：2013-07-09
申请号：US12581694
申请日：2009-10-19
CPC分类号： G06F9/542 , G06F9/3851 , G06F9/3885 , G06F9/4812 , G06F9/4818
摘要： A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.
摘要翻译： 提供了一种方法，信息处理系统和计算机程序产品，用于管理并行处理系统中的应用程序的操作系统干扰。 确定硬件多线程线程到至少一个处理核心的映射，并确定至少一个处理核心的第一和第二组逻辑处理器。 第一组包括至少一个处理核心的逻辑处理器中的至少一个，并且第二组包括至少一个处理核心的逻辑处理器的剩余部分中的至少一个。 处理器仅在至少一个处理核心的第一组逻辑处理器的逻辑处理器上调度应用程序任务。 仅在至少一个处理核心的第二组逻辑处理器的逻辑处理器上调度操作系统干扰事件。
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4.发明申请公开(公告)号：US20080263323A1
公开(公告)日：2008-10-23
申请号：US12102621
申请日：2008-04-14
CPC分类号： G06F15/7867 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3897
摘要： A reconfigurable processor including a plurality of reconfigurable slots, a memory, an instruction queue, a configuration selection unit, and a configuration loader. The plurality of reconfigurable slots are capable of forming reconfigurable execution units. The memory stores a plurality of steering vector processing hardware configurations for configuring the reconfigurable execution units. The instruction queue stores a plurality of instructions to be executed by at least one of the reconfigurable execution units. The configuration selection unit analyzes the dependency of instructions stored in the instruction queue to determine an error metric value for each of the steering vector processing hardware configurations indicative of an ability of a reconfigurable slot configured with the steering vector processing hardware configuration to execute the instructions in the instruction queue, and chooses one of the steering vector processing hardware configurations based upon the error metric values. The configuration loader determines whether one or more of the reconfigurable slots are available and reconfigures at least one of the reconfigurable slots with at least a part of the chosen steering vector processing hardware configuration responsive to at least one of the reconfigurable slots being available.
摘要翻译： 一种可重构处理器，包括多个可重新配置的时隙，存储器，指令队列，配置选择单元和配置加载器。 多个可重新配置的时隙能够形成可重配置的执行单元。 存储器存储用于配置可重配置执行单元的多个导向向量处理硬件配置。 指令队列存储要由可重新配置的执行单元中的至少一个执行的多个指令。 配置选择单元分析存储在指令队列中的指令的依赖性，以确定指示矢量处理硬件配置中的每一个的错误度量值，该配置向量处理硬件配置指示用导向向量处理硬件配置配置的可重配置时隙的能力来执行 指令队列，并且基于错误度量值选择导向向量处理硬件配置之一。 配置加载器确定一个或多个可重新配置的时隙是否可用，并且至少一个可重新配置的时隙与所选择的导向向量处理硬件配置的至少一部分相对应地可重配置时隙中的至少一个可用。
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