公开(公告)号：US5744980A

公开(公告)日：1998-04-28

申请号：US603597

申请日：1996-02-16

申请人： John E. McGowan ,  William C. Plants ,  Joel D. Landry ,  Sinan Kaptanoglu ,  Warren K. Miller

发明人： John E. McGowan ,  William C. Plants ,  Joel D. Landry ,  Sinan Kaptanoglu ,  Warren K. Miller

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17704

摘要： A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors are segmented by user-programmable interconnect elements, and some horizontal and vertical interconnect conductors are connectable by user-programmable interconnect elements located at selected intersections between them. An array of rows and columns of logic function modules each having at least one input and one output is superimposed on the routing channels. The inputs and outputs of the logic function modules are connectable to ones of the interconnect conductors in either or both of the horizontal and vertical routing channels. At least one column of random access memory blocks is disposed in the array. Each random access memory block spans a distance of more than one row of the array such that more than one horizontal routing channel passes therethrough and is connectable to adjacent logic function modules on either side thereof. Each of the random access memory blocks has address inputs, control inputs, data inputs, and data outputs. User-programmable interconnect elements are connected between the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks and selected ones of the interconnect conductors in the horizontal routing channels passing therethrough. Programming circuitry is provided for programming selected ones of the user-programmable interconnect conductors to connect the inputs and outputs of the logic function modules to one another and to the address inputs, control inputs, data inputs, and data outputs of the random access memory blocks.

摘要翻译： 现场可编程门阵列架构包括多个水平和垂直路由通道，每个路由通道包括多个互连导体。 一些互连导体由用户可编程互连元件分段，并且一些水平和垂直互连导体可由位于它们之间的选定交叉处的用户可编程互连元件连接。 每个具有至少一个输入和一个输出的逻辑功能模块的行和列阵列叠加在路由信道上。 逻辑功能模块的输入和输出可连接到水平和垂直路由通道中的一个或两者中的互连导体中的一个。 至少一列随机存取存储器块被布置在阵列中。 每个随机存取存储器块跨越阵列的多于一行的距离，使得多于一个的水平路由信道通过其中并且可连接到其任一侧的相邻逻辑功能模块。 每个随机存取存储块具有地址输入，控制输入，数据输入和数据输出。 用户可编程互连元件连接在随机存取存储器块的地址输入，控制输入，数据输入和数据输出以及通过其中的水平路由通道中的选定的互连导体。 提供了编程电路，用于编程用户可编程互连导体中的所选择的一个以将逻辑功能模块的输入和输出彼此连接，并将随机存取存储器块的地址输入，控制输入，数据输入和数据输出 。

公开(公告)号：US5952852A

公开(公告)日：1999-09-14

申请号：US887380

申请日：1997-07-02

申请人： John E. McGowan ,  William C. Plants ,  Warren K. Miller

发明人： John E. McGowan ,  William C. Plants ,  Warren K. Miller

IPC分类号： G01R31/3185 ,  H03K19/177 ,  H03K19/08

CPC分类号： G01R31/318519

摘要： In a first aspect of the present invention, implementing a fast, wide decode in a field programmable gate array by selecting a test probe circuit associated with a column in the array, selecting at least one logic module associated with the test probe circuit, driving the test probe circuit in the at least one logic module by an output of the at least one logic module, and sensing a logic level in the test probe circuit to determine whether a match in the decode at the inputs of the at least one logic module occurred.In a second aspect of the present invention, implementing a fast, wide decode in a field programmable gate array by selecting a plurality of test probe circuits, each associated with a column in the array, selecting at least one logic module associated with each of the test probe circuits, driving the test probe circuit in the at least one logic module by an output of the at least one logic module, and sensing a logic level in the test probe circuit to determine whether a match in the decode at the inputs of the at least one logic module occurred.

摘要翻译： 在本发明的第一方面，通过选择与阵列中的列相关联的测试探针电路，在现场可编程门阵列中实现快速，宽的解码，选择与测试探针电路相关联的至少一个逻辑模块，驱动 通过所述至少一个逻辑模块的输出在所述至少一个逻辑模块中测试探针电路，并感测所述测试探针电路中的逻辑电平，以确定是否发生在所述至少一个逻辑模块的输入处的解码中的匹配 。 在本发明的第二方面中，通过选择多个测试探针电路来实现现场可编程门阵列中的快速，宽的解码，每个测试探针电路与阵列中的列相关联，选择至少一个逻辑模块 测试探针电路，通过所述至少一个逻辑模块的输出驱动所述至少一个逻辑模块中的所述测试探针电路，并且感测所述测试探针电路中的逻辑电平，以确定在所述至少一个逻辑模块的输入处的解码中是否匹配 发生了至少一个逻辑模块。

公开(公告)号：US06362649B1

公开(公告)日：2002-03-26

申请号：US09286128

申请日：1999-04-02

申请人： John E. McGowan

发明人： John E. McGowan

IPC分类号： H03K19177

CPC分类号： H03K19/17788

摘要： A hybrid integrated circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed input and output buffer circuits, and a first group of input/output pads, wherein one of the input/output pads of the first group is connected to an input of one of the input buffer circuits, and one of the input/output pads of the first group is connected to an output of one of the output buffer circuits. The field programmable gate array portion has programmable digital logic function modules, a second group of input/output pads, interconnect conductors divided into one or more segments, wherein some segments run in a first direction and some segments run in a second direction to form intersections and some segments form intersections with inputs and outputs of the digital logic function modules, the first group of input/output pads, and inputs and outputs of the output and input buffer circuits from the mask programmable portion, and user programmable interconnect elements connected between adjoining ones of the segments in a same one of the interconnect conductors, and between intersections of selected ones the first and second segments, intersections of inputs and outputs of the digital logic function modules and selected interconnect conductors, intersections of the first group of input/output pads and selected ones of the interconnect conductors, intersections with outputs of the input buffer circuits and selected ones of the interconnect conductors, and intersections with the inputs of the output buffer circuits and selected ones of the interconnect conductors.

摘要翻译： 一种混合集成电路架构，包括掩模可编程部分和现场可编程门阵列部分。 掩模可编程部分具有多个掩模编程的输入和输出缓冲器电路以及第一组输入/输出焊盘，其中第一组的输入/输出焊盘之一连接到输入缓冲电路之一的输入端 并且第一组的输入/输出焊盘中的一个连接到一个输出缓冲电路的输出。 现场可编程门阵列部分具有可编程数字逻辑功能模块，第二组输入/输出焊盘，分成一个或多个段的互连导体，其中一些段在第一方向上运行，一些段在第二方向上运行以形成交点 并且一些段形成与数字逻辑功能模块，第一组输入/输出焊盘的输入和输出以及来自掩模可编程部分的输出和输入缓冲器电路的输入和输出以及连接在相邻的用户可编程互连元件 互连导体中相同一个的片段中的一个以及所选择的互连导体中的第一和第二片段的交点之间，数字逻辑功能模块和选定的互连导体的输入和输出的交点，第一组输入/输出 焊盘和选定的互连导体，与输出的交叉点 输入缓冲电路和选定的互连导体，以及与输出缓冲电路和选定的互连导体的输入的交点。

公开(公告)号：US5959466A

公开(公告)日：1999-09-28

申请号：US792482

申请日：1997-01-31

申请人： John E. McGowan

发明人： John E. McGowan

IPC分类号： H03K19/177 ,  H03K7/38

CPC分类号： H03K19/17788

摘要： A hybrid integrate circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed input and output buffer circuits, and a first group of input/output pads, wherein one of the input/output pads of the first group is connected to an input of one of the input buffer circuits, and one of the input/output pads of the first group is connected to an output of one of the output buffer circuits. The field programmable gate array portion has programmable digital logic function modules, a second group of input/output pads, interconnect conductors divided into one or more segments, wherein some segments run in a first direction and some segments run in a second direction to form intersections and some segments form intersections with inputs and outputs of the digital logic function modules, the first group of input/output pads, and inputs and outputs of the output and input buffer circuits from the mask programmable portion, and user programmable interconnect elements connected between adjoining ones of the segments in a same one of the interconnect conductors, and between intersections of selected ones the first and second segments, intersections of inputs and outputs of the digital logic function modules and selected interconnect conductors, intersections of the first group of input/output pads and selected ones of the interconnect conductors, intersections with outputs of the input buffer circuits and selected ones of the interconnect conductors, and intersections with the inputs of the output buffer circuits and selected ones of the interconnect conductors.

摘要翻译： 一种混合集成电路架构，其包括掩模可编程部分和现场可编程门阵列部分。 掩模可编程部分具有多个掩模编程的输入和输出缓冲器电路以及第一组输入/输出焊盘，其中第一组的输入/输出焊盘之一连接到输入缓冲电路之一的输入端 并且第一组的输入/输出焊盘中的一个连接到一个输出缓冲电路的输出。 现场可编程门阵列部分具有可编程数字逻辑功能模块，第二组输入/输出焊盘，分成一个或多个段的互连导体，其中一些段在第一方向上运行，一些段在第二方向上运行以形成交点 并且一些段形成与数字逻辑功能模块，第一组输入/输出焊盘的输入和输出以及来自掩模可编程部分的输出和输入缓冲器电路的输入和输出以及连接在相邻的用户可编程互连元件 互连导体中相同一个的片段中的一个以及所选择的互连导体中的第一和第二片段的交点之间，数字逻辑功能模块和选定的互连导体的输入和输出的交点，第一组输入/输出 焊盘和选定的互连导体，与输出的交叉点 输入缓冲电路和选定的互连导体，以及与输出缓冲电路和选定的互连导体的输入的交点。

公开(公告)号：US5821776A

公开(公告)日：1998-10-13

申请号：US792902

申请日：1997-01-31

申请人： John E. McGowan

发明人： John E. McGowan

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17732 ,  H03K19/1778

摘要： A mixed signal integrated circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed analog function circuits, and a first group of input/output pads, wherein one of the input/output pads of the first group is connected to an input of one of the analog function circuits, and one of the input/output pads of the first group is connected to an output of one of the analog function circuits. The field programmable gate array portion has programmable digital logic function modules, a second group of input/output pads, interconnect conductors divided into one or more segments, wherein some segments run in a first direction and some segments run in a second direction to form intersections and some segments form intersections with inputs and outputs of the digital logic function modules, the first group of input/output pads, and inputs and outputs of the analog function circuits from the mask programmable analog portion, and user programmable interconnect elements connected between adjoining ones of the segments in a same one of the interconnect conductors, and between intersections of selected ones the first and second segments, intersections of inputs and outputs of the digital logic function modules and selected interconnect conductors, intersections of the first group of input/output pads and selected ones of the interconnect conductors, intersections with outputs of the analog function circuits and selected ones of the interconnect conductors, and intersections with the inputs of the analog function circuits and selected ones of the interconnect conductors.

摘要翻译： 一种包括掩模可编程部分和现场可编程门阵列部分的混合信号集成电路架构。 掩模可编程部分具有多个掩模编程的模拟功能电路和第一组输入/输出焊盘，其中第一组的输入/输出焊盘之一连接到模拟功能电路中的一个的输入，以及 第一组的输入/输出焊盘之一连接到模拟功能电路之一的输出。 现场可编程门阵列部分具有可编程数字逻辑功能模块，第二组输入/输出焊盘，分成一个或多个段的互连导体，其中一些段在第一方向上运行，一些段在第二方向上运行以形成交点 并且一些段形成与数字逻辑功能模块的输入和输出，第一组输入/输出焊盘以及来自掩模可编程模拟部分的模拟功能电路的输入和输出以及连接在相邻的模块之间的用户可编程互连元件的交点 在同一个互连导体中的段之间以及在第一和第二段之间的交叉点之间，数字逻辑功能模块和所选择的互连导体的输入和输出的交点，第一组输入/输出焊盘 和选定的互连导体，与a的输出相交 nalog功能电路和选定的互连导体，以及与模拟功能电路和所选互连导体的输入的交点。