公开(公告)号：US20070184619A1

公开(公告)日：2007-08-09

申请号：US11346662

申请日：2006-02-03

申请人： John Hergenrother ,  Zhibin Ren ,  Dinkar Singh ,  Jeffrey Sleight

发明人： John Hergenrother ,  Zhibin Ren ,  Dinkar Singh ,  Jeffrey Sleight

IPC分类号： H01L21/336

CPC分类号： H01L21/28097 ,  H01L21/26506 ,  H01L21/28185 ,  H01L21/7624 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.

摘要翻译： 用于选择性地将电荷放置到栅极堆叠中的器件和方法包括形成包括邻近晶体管沟道和栅极导体的栅极电介质的栅极堆叠，并形成用于晶体管操作的掺杂区域。 在掺杂区域和栅极叠层上沉积富含钝化元素的层，并且从所选择的晶体管去除富含钝化元件的层。 富含钝化元件的层比退火以驱动钝化元件，以增加在存在钝化元件的层的晶体管上的晶体管沟槽处或附近的电荷浓度。 去除富含钝化元素的层。

公开(公告)号：US20070158743A1

公开(公告)日：2007-07-12

申请号：US11329490

申请日：2006-01-11

申请人： Leland Chang ,  David Fried ,  John Hergenrother ,  Ghavam Shahidi ,  Jeffrey Sleight

发明人： Leland Chang ,  David Fried ,  John Hergenrother ,  Ghavam Shahidi ,  Jeffrey Sleight

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/7843

摘要： The present invention provides a semiconducting device structure including a thin SOI region, wherein the SOI device is formed with an optional single thin diffusion, i.e., offset, spacer and a single diffusion implant. The device silicon thickness is thin enough to permit the diffusion implants to abut the buried insulator but thick enough to form a contacting silicide. Stress layer liner films are used both over nFET and pFET device regions to enhance performance.

摘要翻译： 本发明提供了一种包括薄SOI区域的半导体器件结构，其中SOI器件形成有可选的单个薄扩散，即偏移，间隔物和单个扩散注入。 器件硅厚度足够薄以允许扩散植入物邻接埋入的绝缘体，但是足够厚以形成接触硅化物。 应力层衬垫膜都用于nFET和pFET器件区域，以提高性能。

公开(公告)号：US20070099367A1

公开(公告)日：2007-05-03

申请号：US11612309

申请日：2006-12-18

申请人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

摘要翻译： 本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。 本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。 本发明的另一方面涉及形成本发明的半导体材料的方法。 本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。

公开(公告)号：US20080044966A1

公开(公告)日：2008-02-21

申请号：US11924024

申请日：2007-10-25

申请人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/8234

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

公开(公告)号：US20080044987A1

公开(公告)日：2008-02-21

申请号：US11924015

申请日：2007-10-25

申请人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/20

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

公开(公告)号：US20050145837A1

公开(公告)日：2005-07-07

申请号：US10980220

申请日：2004-11-03

申请人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Massimo Fischetti ,  John Hergenrother ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Paul Solomon ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

摘要翻译： 本发明提供了具有增强的电子和空穴迁移率的半导体材料，其包含具有<110>晶体取向和双轴压缩应变的含Si层。 本文中使用的术语“双轴压应力”来描述在制造半导体材料期间由含Si层引起的纵向压应力和横向应力引起的净应力。 本发明的另一方面涉及形成本发明的半导体材料的方法。 本发明的方法包括提供含硅<110>层的步骤; 并在含硅<110>层中产生双轴应变。