Scalable processor to processor and processor-to-I/O interconnection
network and method for parallel processing arrays
    1.
    发明授权
    Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays 失效
    可扩展处理器到处理器和处理器到I / O互连网络和并行处理阵列的方法

    公开(公告)号:US5280474A

    公开(公告)日:1994-01-18

    申请号:US461492

    申请日:1990-01-05

    CPC分类号: G06F15/17393

    摘要: A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.

    摘要翻译: 公开了一种具有全局路由器网络的大规模并行计算机系统(500),其中流水线寄存器在空间上分布以增加全局路由器网络的消息传送速度。 全局路由器网络包括用于处理器到I / O(1700)消息传递的扩展抽头,以便I / O消息带宽与处理器间消息带宽相匹配。 路由开启消息分组包括与转向比特均匀对待的协议比特。 路由开启分组还包括冗余地址比特,用于向全球路由器网络内的路由器芯片赋予多交叉形状个性。 还公开了用于空间上支持大规模并行系统和全局路由器网络的处理器(700)的结构和方法。