Scalable processor to processor and processor-to-I/O interconnection
network and method for parallel processing arrays
    1.
    发明授权
    Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays 失效
    可扩展处理器到处理器和处理器到I / O互连网络和并行处理阵列的方法

    公开(公告)号:US5280474A

    公开(公告)日:1994-01-18

    申请号:US461492

    申请日:1990-01-05

    CPC分类号: G06F15/17393

    摘要: A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.

    摘要翻译: 公开了一种具有全局路由器网络的大规模并行计算机系统(500),其中流水线寄存器在空间上分布以增加全局路由器网络的消息传送速度。 全局路由器网络包括用于处理器到I / O(1700)消息传递的扩展抽头,以便I / O消息带宽与处理器间消息带宽相匹配。 路由开启消息分组包括与转向比特均匀对待的协议比特。 路由开启分组还包括冗余地址比特,用于向全球路由器网络内的路由器芯片赋予多交叉形状个性。 还公开了用于空间上支持大规模并行系统和全局路由器网络的处理器(700)的结构和方法。

    Scalable processor to processor and processor to I/O interconnection
network and method for parallel processing arrays
    2.
    发明授权
    Scalable processor to processor and processor to I/O interconnection network and method for parallel processing arrays 失效
    可扩展处理器到处理器和处理器到I / O互连网络和并行处理阵列的方法

    公开(公告)号:US5598408A

    公开(公告)日:1997-01-28

    申请号:US182250

    申请日:1994-01-14

    CPC分类号: G06F15/17393

    摘要: A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.

    摘要翻译: 公开了一种具有全局路由器网络的大规模并行计算机系统,其中流水线寄存器在空间上分布以增加全局路由器网络的消息传送速度。 全局路由器网络包括用于处理器到I / O消息传递的扩展抽头,以便I / O消息带宽与处理器间消息带宽相匹配。 路由开启消息分组包括与转向比特均匀对待的协议比特。 路由开启分组还包括冗余地址比特,用于向全球路由器网络内的路由器芯片赋予多交叉形状个性。 还公开了用于空间支持大规模并行系统和全局路由器网络的处理器的结构和方法。

    Parallel processor memory transfer system using parallel transfers
between processors and staging registers and sequential transfers
between staging registers and memory
    3.
    发明授权
    Parallel processor memory transfer system using parallel transfers between processors and staging registers and sequential transfers between staging registers and memory 失效
    并行处理器存储器传输系统使用处理器和分段寄存器之间的并行传输,以及分级寄存器和存储器之间的顺序传输

    公开(公告)号:US5581777A

    公开(公告)日:1996-12-03

    申请号:US400411

    申请日:1995-03-03

    摘要: A massively parallel processor is provided with a plurality of clusters. Each cluster includes a plurality of processor elements ("PEs") and a cluster memory. Each PE of the cluster has associated with it an address register, a stage register, an error register, a PE enable flag, a memory flag, and a grant request flag. A cluster data bus and an error bus connects each of the stage registers and error registers of the cluster to the memory. The grant request flags of the cluster are interconnected by a polling network, which polls only one of the grant request flags at a time. In response to a signal on the polling network and the state of the associated memory flag, the grant request flag determines an I/O operation between the associated data register and the cluster memory over the cluster data bus. Both data and error bits are associated with respective processor elements. The sequential memory operations proceed in parallel with parallel processor operations. The sequential memory operations also may be queued. Addressing modes include direct and indirect. In direct address mode, a PE addresses its own address space by appending its PE number to a broadcast partial address. The broadcast partial address is furnished over a broadcast bus, and the PE number is furnished on a cluster address bus. In indirect address mode, a PE addresses either its own address space or that of other PEs in its cluster by locally calculating a partial address, then appending to it either its own PE number or that of another PE in its cluster. The full address is furnished over the cluster address bus.

    摘要翻译: 大规模并行处理器具有多个簇。 每个群集包括多个处理器元件(“PE”)和群集存储器。 集群的每个PE与它相关联地址寄存器,阶段寄存器,错误寄存器,PE使能标志,存储器标志和授权请求标志。 集群数据总线和错误总线将集群的每个阶段寄存器和错误寄存器连接到存储器。 集群的授权请求标志由轮询网络相互连接,轮询网络一次仅轮询授权请求标志中的一个。 响应于轮询网络上的信号和相关联的存储器标志的状态,授权请求标志通过集群数据总线确定相关联的数据寄存器和集群存储器之间的I / O操作。 数据和错误位都与相应的处理器元件相关联。 顺序存储器操作与并行处理器操作并行进行。 顺序存储器操作也可以排队。 寻址模式包括直接和间接。 在直接地址模式下,PE通过将其PE号附加到广播部分地址来寻址其自己的地址空间。 广播部分地址通过广播总线提供,PE号码在集群地址总线上提供。 在间接寻址模式下,PE通过本地计算部分地址来寻址其自身的地址空间或其簇中的其他PE,然后将其自身的PE号或其簇中的另一个PE附加到该地址空间。 整个地址通过集群地址总线提供。

    Input/output system for parallel processing arrays
    4.
    发明授权
    Input/output system for parallel processing arrays 失效
    用于并行处理阵列的输入/输出系统

    公开(公告)号:US5243699A

    公开(公告)日:1993-09-07

    申请号:US802944

    申请日:1991-12-06

    IPC分类号: G06F15/173 G06F15/80

    CPC分类号: G06F15/8007 G06F15/17393

    摘要: A massively parallel processor includes an array of processor elements (20), of PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has address and data buses (52) to the I/O devices (80, 82) and other address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the router ports (e.g. S2.sub.-- 0.sub.-- X0) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of router lines (32) and the relatively few buses (52) to the I/O devices.

    摘要翻译: 大规模并行处理器包括PE的处理器元件阵列(20)和用于I / O通信和用于PE至PE通信的多级路由器互连网络(30)。 用于大规模并行处理器的I / O系统(10)基于具有到I / O设备(80,82)的地址和数据总线(52)的全局共享的可寻址I / O RAM缓冲存储器(50) 耦合到路由器I / O元件阵列(40)的其它地址和数据总线(42)。 路由器I / O元件阵列又耦合到路由器互连网络的第二级(430)的路由器端口(例如,S2-0-X0)。 路由器I / O阵列提供大量路由器线路(32)和相对较少的总线(52)到I / O设备之间的拐角转换。

    Parallel processor system with highly flexible local control capability,
including selective inversion of instruction signal and control of bit
shift amount
    5.
    发明授权
    Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount 失效
    并行处理器系统具有高度灵活的本地控制能力,包括指令信号的选择性反转和位移量的控制

    公开(公告)号:US5542074A

    公开(公告)日:1996-07-30

    申请号:US965938

    申请日:1992-10-22

    IPC分类号: G06F15/80 G06F15/76

    摘要: A parallel processor system which operates in a single-instruction multiple-data mode has a highly flexible local control capability for enabling the system to operate fast. The system contains an array of processing elements or PEs (12.sub.1 -12.sub.N) that process respective sets of data according to instructions supplied from a global control unit (20). Each instruction is furnished simultaneously to all the PEs. One local control feature (52) entails selectively inverting certain instruction signals according to a data-dependent signal. Another local control feature (48) involves controlling the amount of a bit shift in a barrel shifter (98) according to a data-dependent signal.

    摘要翻译: 以单指令多数据模式运行的并行处理器系统具有高度灵活的本地控制能力,使系统能够快速运行。 该系统包含一系列处理元件或PE(121-12N),根据从全局控制单元(20)提供的指令处理相应的数据集。 每个指令同时提供给所有的PE。 一个本地控制特征(52)需要根据数据相关信号选择性地反转某些指令信号。 另一个本地控制特征(48)涉及根据数据相关信号来控制桶形移位器(98)中的位移的量。

    Cephalosporin compounds
    6.
    发明授权
    Cephalosporin compounds 失效
    CEPHALOSPORIN化合物

    公开(公告)号:US5202315A

    公开(公告)日:1993-04-13

    申请号:US494163

    申请日:1990-03-15

    CPC分类号: C07D501/36

    摘要: The present invention relates to new cephalosporin compounds of the formula(I), pharmaceutically acceptable non-toxic salts thereof, and physiologically hydrolyzable esters and solvates thereof, which have potent and broad antibacterial activities ##STR1## wherein R.sup.1 is a C.sub.1.about.4 alkyl, C.sub.3.about.4 alkenyl, C.sub.3.about.4 alkynyl group, or --C(R.sup.a)(R.sup.b)CO.sub.2 H.sub.1 wherein R.sup.a and R.sup.b are the same or different, and each is a hydrogen atom or a C.sub.1.about.4 alkyl group, or R.sup.a and R.sup.b form a C.sub.3.about.7 cycloalkyl group with the carbon atom to which they are linked;R.sup.2 is a C.sub.1.about.4 alkyl, C.sub.3.about.4 alkenyl or C.sub.3.about.4 cycloalkyl group, a substituted or unsubstituted amino group, or a substituted or unsubstituted phenyl group;R.sup.3 is hydrogen or a C.sub.1.about.4 alkyl group; andQ is N or CH.The invention further relates to a process for preparing said compounds, and to pharamaceutical compositions containing said compounds.

    Process for preparing hydroxyl polyester for use in a powder coating and
a powder coating composition thereof
    7.
    发明授权
    Process for preparing hydroxyl polyester for use in a powder coating and a powder coating composition thereof 失效
    制备用于粉末涂料的羟基聚酯及其粉末涂料组合物的方法

    公开(公告)号:US4975513A

    公开(公告)日:1990-12-04

    申请号:US291613

    申请日:1988-12-29

    摘要: A crystalline polyester resin derived from the reaction between a prepolymer and trimellitic anhydride in an amount of less than 10 wt % of the prepolymer where prepolymer as an intermediate product formed from the reaction between an alcohol mixture containing at least 40 mole % ethylene glycol and at least 30 mol % neopentyl glycol, and an acid mixture containing terephthalic acid or dimethyl terephthalate of at least 40 mole % and a linear dicarboxylic acid, or between an alcohol mixture containing 100 wt % terephthalic acid or dimethyl terephthalate. The crystalline polyester resin is very suitable for use in powder coating compositions and has a hyodroxyl number of 20 to 100, an average molecular weight of 1000 to 3500 and a melt viscosity at 160.degree. C. of 500 to 4000 cps as well as the characteristics of dense, regular, and repetitive structure.

    摘要翻译: 衍生自预聚物和偏苯三酸酐之间的反应的结晶聚酯树脂,其量小于其中预聚物作为中间产物的预聚物的量小于10重量%,所述预聚物是由含有至少40摩尔%乙二醇的醇混合物和 至少30摩尔%的新戊二醇,以及含有至少40摩尔%的对苯二甲酸或对苯二甲酸二甲酯和线性二羧酸的酸混合物,或含有100重量%对苯二甲酸或对苯二甲酸二甲酯的醇混合物。 结晶性聚酯树脂非常适用于粉末涂料组合物,其羟基数为20〜100,平均分子量为1000〜3500,在160℃下的熔体粘度为500〜4000cps,特性 密集,规则和重复的结构。

    Cephalosporin compounds
    8.
    发明授权
    Cephalosporin compounds 失效
    头孢菌素化合物

    公开(公告)号:US4971962A

    公开(公告)日:1990-11-20

    申请号:US350617

    申请日:1989-05-11

    CPC分类号: C07D501/00 Y02P20/55

    摘要: The present invention relates to novel cephalosporin compounds having high antimicrobial activity, which are shown by the formula(I), and to a process for preparing them ##STR1## wherein R.sup.1 is a hydrogen atom or an amino protecting group;R.sup.2 is acetoxy; andR.sup.3 is a hydrogen atom or a carboxyl protecting group (wherein when R.sup.2 contains quaternary ammonium, r.sup.2 and R.sup.3 may form a zwitter ion).The present invention also relates to the non-toxic and pharmaceutically acceptable salts of the cephalosporin compounds of the formula (I). Also described are compositions containing the antibiotics according to the present invention.

    摘要翻译: 本发明涉及具有高抗微生物活性的新型头孢菌素化合物,其由式(I)表示,及其制备方法其中R 1为氢原子或氨基保护基; R2是乙酰氧基; 并且R 3是氢原子或羧基保护基(其中当R 2含有季铵时,r 2和R 3可以形成一个两性离子)。 本发明还涉及式(I)的头孢菌素化合物的无毒和药学上可接受的盐。 还描述了含有根据本发明的抗生素的组合物。

    Cephalosporin compounds
    10.
    发明授权
    Cephalosporin compounds 失效
    头孢菌素化合物

    公开(公告)号:US5462935A

    公开(公告)日:1995-10-31

    申请号:US971986

    申请日:1993-02-10

    CPC分类号: C07D501/00

    摘要: The present invention provides a cephalosporin compound represented by formulas (I-S) and (I-R) ##STR1## wherein: R.sup.1 is a C.sub.1-4 alkyl, C.sub.3-4 alkenyl, C.sub.3-4 cycloalkyl, amino optionally substituted with a C.sub.1-4 alkyl radical, phenyl, or 2-,4- or 6- substituted phenyl group with two or fewer substitutents chosen from C.sub.1-4 alkyl, C.sub.1-3 alkoxy, halogen and hydroxy radicals;R.sup.2 is hydrogen or a C.sub.1-4 alkyl group;R.sup.a and R.sup.b, which should be different from each other, are hydrogen or a C.sub.1-4 alkyl group; andQ is N or CH,and the pharmaceutically acceptable non-toxic salts, physiologically hydrolyzable esters, hydrates and solvates thereof, which possess potent and broad antibacterial activities. The invention also provides processes for preparing these compounds and to pharmaceutical compositions containing them as active ingredients.

    摘要翻译: 本发明提供由式(IS)和(1R)表示的头孢菌素化合物。其中:R1是C1-4烷基,C3-4链烯基,C3-4环烷基,氨基 任选被C1-4烷基,苯基或2-,4-或6-取代的苯基取代,具有两个或更少个选自C 1-4烷基,C 1-3烷氧基,卤素和羟基的取代基; R2是氢或C1-4烷基; 应该彼此不同的R a和R b是氢或C 1-4烷基; 和Q是N或CH,以及其药学上可接受的无毒盐,生理上可水解的酯,水合物和溶剂合物,其具有有效和广泛的抗菌活性。 本发明还提供了制备这些化合物的方法和含有它们作为活性成分的药物组合物。