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    Statistics data collection mechanism for distributed, high-speed data processing environments
    1.
    发明授权
    Statistics data collection mechanism for distributed, high-speed data processing environments 有权
    统计数据采集机制，用于分布式，高速数据处理环境

    公开(公告)号：US07187683B1

    公开(公告)日：2007-03-06

    申请号：US10013386

    申请日：2001-12-07

    申请人： John Sandoval ,  Virendra Patel ,  Frederic Mathieu ,  Jayakumar Jayakumar ,  Rohit Sharma

    发明人： John Sandoval ,  Virendra Patel ,  Frederic Mathieu ,  Jayakumar Jayakumar ,  Rohit Sharma

    IPC分类号： H04L12/28

    CPC分类号： H04L41/142 ,  H04L43/04

    摘要： A statistics data collection mechanism for distributed, high-speed data processing environments is described. According to one embodiment, an update message containing statistics data related to a data packet carried along a virtual connection is assembled and the update message is then transmitted to a statistics collection engine for further processing. According to another embodiment, the update message is received from one or more processing devices, and multiple counters are then updated to store the statistics data.

    摘要翻译： 描述了用于分布式高速数据处理环境的统计数据收集机制。 根据一个实施例，组装包含与虚拟连接携带的数据分组有关的统计数据的更新消息，并且将更新消息发送到统计收集引擎用于进一步处理。 根据另一个实施例，从一个或多个处理设备接收更新消息，然后更新多个计数器以存储统计数据。

    Accessing multiple copies of RAM distributed throughout an ASIC/FPGA and maintaining their content consistency
    2.
    发明授权
    Accessing multiple copies of RAM distributed throughout an ASIC/FPGA and maintaining their content consistency 有权
    访问分布在整个ASIC / FPGA中的多个RAM副本，并保持其内容的一致性

    公开(公告)号：US07275129B1

    公开(公告)日：2007-09-25

    申请号：US10768925

    申请日：2004-01-30

    申请人： Quang Cao Phung ,  John Sandoval ,  Kent Wayne Wendorf

    发明人： Quang Cao Phung ,  John Sandoval ,  Kent Wayne Wendorf

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1663 ,  G06F11/167

    摘要： A system and method for writing the same data field to multiple RAM copies during a single write cycle that fans out write data, address data, and control data to multiple RAMs. The multiple copies of data held at the same address in the multiple RAM copies are also read during a single write cycle and the data from each RAM copy is concatenated into a single word that is read during a single read cycle.

    摘要翻译： 一种用于在单个写入周期内将相同数据字段写入多个RAM副本的系统和方法，用于将写数据，地址数据和控制数据写入多个RAM。 保持在多个RAM副本中的相同地址的数据的多个副本也将在单个写周期期间被读取，并且来自每个RAM副本的数据被连接成在单个读取周期期间读取的单个字。

    Shared buffer switch interface
    3.
    发明授权
    Shared buffer switch interface 有权
    共享缓冲区交换机接口

    公开(公告)号：US07417986B1

    公开(公告)日：2008-08-26

    申请号：US09947184

    申请日：2001-09-04

    申请人： John Sandoval ,  Matt Noel ,  Eugene Wang

    发明人： John Sandoval ,  Matt Noel ,  Eugene Wang

    IPC分类号： H04L12/28

    CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L2012/5642 ,  H04L2012/5681 ,  H04L2012/5682

    摘要： A system and method for using a single shared buffer to service multiple destinations for a telecommunications switch is disclosed. Upon receiving a cell of data to be sent to a destination, an interface stores the cell in a shared buffer. The address of the cell in the buffer is stored in a queue array. The address of the buffer address in the queue array is stored in a head array and a tail array. A threshold register tracks the global threshold for the total number of cells in the shared buffer and a destination threshold for each destination. The buffer can broadcast a data cell to a single location or send the same cell to multiple locations.

    摘要翻译： 公开了一种用于使用单个共享缓冲器来为电信交换机服务多个目的地的系统和方法。 在接收到要发送到目的地的数据单元时，接口将该单元存储在共享缓冲器中。 缓冲区中单元格的地址存储在队列数组中。 队列数组中缓冲区地址的地址存储在头数组和尾数组中。 阈值寄存器跟踪共享缓冲区中的单元总数的全局阈值和每个目的地的目标阈值。 缓冲器可以将数据单元广播到单个位置或将相同的单元发送到多个位置。