公开(公告)号：US20080013450A1

公开(公告)日：2008-01-17

申请号：US11732708

申请日：2007-04-03

申请人： John Worley ,  Matthew Gerlach

发明人： John Worley ,  Matthew Gerlach

IPC分类号： H04L12/56

CPC分类号： G06F16/2477

摘要： Embodiments of the present invention are directed to computationally efficient timer-queue management. In one embodiment of the present invention, a timer queue is implemented as a circular-timer queue, containing timers, or time-associated data objects, due to expire in a relatively short period of time, and a second queue or list of timers or time-associated data objects, referred to as the “later queue,” containing timers or time-associated data objects due to expire after a period of time longer than the period of time during which the timers or timer-associated data objects on the circular-timer queue are due to expire. At generally regular intervals, as timers or time-associated data objects are removed from the circular-timer queue, timers or time-associated data objects are transferred from the later queue to the circular-timer queue.

摘要翻译： 本发明的实施例涉及计算上有效的定时器队列管理。 在本发明的一个实施例中，定时器队列被实现为循环定时器队列，其包含定时器或时间相关联的数据对象，由于在相对较短的时间段内到期，并且第二队列或定时器或 被称为“后期队列”的时间相关数据对象包含定时器或与时间有关的数据对象，由于在一段时间之后到期时间长于循环周期内的定时器或定时器相关数据对象的时间段 -timer队列将到期。 以一般的间隔时间，由于定时器或与时间有关的数据对象从循环定时器队列中移除，定时器或与时间相关的数据对象从稍后队列传送到循环定时器队列。

公开(公告)号：US20130155781A1

公开(公告)日：2013-06-20

申请号：US13327693

申请日：2011-12-15

申请人： Venkata Kottapalli ,  Scott Pitkethly ,  Christian Klingner ,  Matthew Gerlach

发明人： Venkata Kottapalli ,  Scott Pitkethly ,  Christian Klingner ,  Matthew Gerlach

IPC分类号： G11C7/10

CPC分类号： G11C7/1072 ,  H03K3/012

摘要： A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.

摘要翻译： 一种存储电路，其中第一数据输入的电平响应于接收到的时钟脉冲而迅速地出现在输出端。 该电路包括由时钟脉冲触发并被配置为接收第一数据输入并驱动第二数据输入的触发器。 电路还包括由时钟脉冲驱动的第一控制输入，由触发器驱动的第二控制输入和被配置为接收第一和第二数据输入以及第一和第二控制输入的选择逻辑。 选择逻辑被配置为根据第一和第二控制输入将存储器电路的输出驱动到第一数据输入或第二数据输入的电平。

公开(公告)号：US08848458B2

公开(公告)日：2014-09-30

申请号：US13327693

申请日：2011-12-15

申请人： Venkata Kottapalli ,  Scott Pitkethly ,  Christian Klingner ,  Matthew Gerlach

发明人： Venkata Kottapalli ,  Scott Pitkethly ,  Christian Klingner ,  Matthew Gerlach

IPC分类号： G11C7/10

CPC分类号： G11C7/1072 ,  H03K3/012

摘要： A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.

摘要翻译： 一种存储电路，其中第一数据输入的电平响应于接收到的时钟脉冲而迅速地出现在输出端。 该电路包括由时钟脉冲触发并被配置为接收第一数据输入并驱动第二数据输入的触发器。 电路还包括由时钟脉冲驱动的第一控制输入，由触发器驱动的第二控制输入和被配置为接收第一和第二数据输入以及第一和第二控制输入的选择逻辑。 选择逻辑被配置为根据第一和第二控制输入将存储器电路的输出驱动到第一数据输入或第二数据输入的电平。

公开(公告)号：US20070064124A1

公开(公告)日：2007-03-22

申请号：US11516809

申请日：2006-09-05

申请人： Shekhar Kirani ,  Matthew Gerlach ,  Timothy Genske ,  David Vogel ,  William Swinton ,  Venkat Easwar ,  Eric Bodnar

发明人： Shekhar Kirani ,  Matthew Gerlach ,  Timothy Genske ,  David Vogel ,  William Swinton ,  Venkat Easwar ,  Eric Bodnar

IPC分类号： H04N9/68

CPC分类号： G06T9/007 ,  H04L67/04 ,  H04L67/06 ,  H04L67/1095

摘要： A media spooler system is described that provides a methodology for efficient transmission of media content from client devices, such transmission of digital images from wireless digital cameras. The media spooler or gateway addresses wireless transmission problems by acting as a protocol gateway between a thin-client device and a target host or server (supported by a server infrastructure). More particularly, the media spooler of the present invention acts as a protocol gateway between thin-client devices (e.g., “mobile visual communicator” in the form of a wireless digital camera) and server infrastructure (e.g., server-based computer systems or “Web servers” of a photographic service provider). This task entails accepting multiple, simultaneous connections from various client devices (e.g., wireless digital cameras), extracting information from those devices (e.g., digital photographs or other media content), and then uploading that information to the target server infrastructure. In basic operation, the media spooler queries each client device for the information (e.g., media, such as pictures) the client device thinks should uploaded, and then the media spooler queries the server infrastructure for the subset of pictures that have not been already uploaded. This improved coordination or synchronization of information between a device and target host allows for efficient recovery of dropped cellular data calls by essentially allowing the media spooler to “pick up where it left off.”

摘要翻译： 描述了一种媒体假脱机系统，其提供用于从客户端设备有效地传输媒体内容的方法，例如来自无线数字照相机的数字图像的传输。 媒体假脱机程序或网关通过充当瘦客户机设备与目标主机或服务器（由服务器基础设施支持）之间的协议网关来解决无线传输问题。 更具体地说，本发明的媒体假脱机器作为瘦客户端设备（例如，无线数字照相机形式的“移动可视通信器”）和服务器基础设施（例如基于服务器的计算机系统或“ 摄影服务提供商的Web服务器“）。 该任务需要接受来自各种客户端设备（例如，无线数字照相机）的多个同时连接，从那些设备提取信息（例如，数字照片或其他媒体内容），然后将该信息上传到目标服务器基础设施。 在基本操作中，媒体后台处理程序向每个客户端设备查询客户端设备认为应上传的信息（例如，媒体，如图片），然后介质后台处理程序查询服务器基础结构以获得尚未上传的图片子集 。 这种改进的设备和目标主机之间的信息的协调或同步允许通过基本上允许媒体假脱机程序“拾取其停留在何处”来有效地恢复丢弃的蜂窝数据呼叫。

公开(公告)号：US09911470B2

公开(公告)日：2018-03-06

申请号：US13447037

申请日：2012-04-13

申请人： Venkata Kottapalli ,  Scott Pitkethly ,  Christian Klingner ,  Matthew Gerlach

发明人： Venkata Kottapalli ,  Scott Pitkethly ,  Christian Klingner ,  Matthew Gerlach

IPC分类号： G11C7/10 ,  H03K3/012

CPC分类号： G11C7/1072 ,  H03K3/012

摘要： A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.

公开(公告)号：US20130155783A1

公开(公告)日：2013-06-20

申请号：US13447037

申请日：2012-04-13

申请人： Venkata Kottapalli ,  Scott Pitkethly ,  Christian Klingner ,  Matthew Gerlach

发明人： Venkata Kottapalli ,  Scott Pitkethly ,  Christian Klingner ,  Matthew Gerlach

IPC分类号： G11C7/10

CPC分类号： G11C7/1072 ,  H03K3/012

摘要： A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.

摘要翻译： 在接收时钟脉冲时立即在数据输出端呈现输入数据的存储器电路包括上游和下游存储器逻辑和选择逻辑。 上游存储器逻辑被配置为在接收时钟脉冲时锁存输入数据。 下游存储器逻辑被配置为存储锁存的输入数据。 选择逻辑被配置为根据上游存储器逻辑是否锁存了输入数据，在输入数据被锁存之前从输入数据导出的暴露逻辑电平以及输入数据之后的锁存输入数据暴露逻辑电平 锁定