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公开(公告)号：US20130155781A1
公开(公告)日：2013-06-20
申请号：US13327693
申请日：2011-12-15
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , H03K3/012
摘要： A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.
摘要翻译： 一种存储电路，其中第一数据输入的电平响应于接收到的时钟脉冲而迅速地出现在输出端。 该电路包括由时钟脉冲触发并被配置为接收第一数据输入并驱动第二数据输入的触发器。 电路还包括由时钟脉冲驱动的第一控制输入，由触发器驱动的第二控制输入和被配置为接收第一和第二数据输入以及第一和第二控制输入的选择逻辑。 选择逻辑被配置为根据第一和第二控制输入将存储器电路的输出驱动到第一数据输入或第二数据输入的电平。
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2.发明申请Repeater circuit having different operating and reset voltage ranges, and methods thereof 有权具有不同工作和复位电压范围的中继器电路及其方法公开(公告)号：US20050270069A1
公开(公告)日：2005-12-08
申请号：US10879808
申请日：2004-06-28
IPC分类号： H03K19/003 , H03K19/017 , H04L25/24 , H03K19/094
CPC分类号： H03K19/01721 , H03K19/00361 , H04L25/242
摘要： A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second subcircuit causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and drive the output to a low state to assist in the falling transition. A third subcircuit resets elements of the first subcircuit. The first subcircuit operates above a first voltage threshold and the third subcircuit operates below the first voltage threshold. A fourth subcircuit resets elements of the second subcircuit. The second subcircuit operates below a second voltage threshold and the fourth subcircuit operates above the second voltage threshold.
摘要翻译： 用于辅助线上信号转换的电路及其方法。 第一分支电路使得耦合到电路的输出的第一晶体管在上升转变期间导通，并将输出驱动到高状态以辅助上升转变。 第二分支电路使得耦合到电路的输出的第二晶体管在下降转变期间导通，并且将输出驱动到低状态以辅助下降转换。 第三个分支电路重置第一个子电路的元素。 第一分支电路工作在第一电压阈值以上，第三子电路工作在第一电压阈值以下。 第四个分支电路复位第二个子电路的元素。 第二分支电路工作在第二电压阈值以下，第四分支电路工作在第二电压阈值以上。
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公开(公告)号：US08848458B2
公开(公告)日：2014-09-30
申请号：US13327693
申请日：2011-12-15
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , H03K3/012
摘要： A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.
摘要翻译： 一种存储电路，其中第一数据输入的电平响应于接收到的时钟脉冲而迅速地出现在输出端。 该电路包括由时钟脉冲触发并被配置为接收第一数据输入并驱动第二数据输入的触发器。 电路还包括由时钟脉冲驱动的第一控制输入，由触发器驱动的第二控制输入和被配置为接收第一和第二数据输入以及第一和第二控制输入的选择逻辑。 选择逻辑被配置为根据第一和第二控制输入将存储器电路的输出驱动到第一数据输入或第二数据输入的电平。
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4.发明授权Repeater circuit having different operating and reset voltage ranges, and methods thereof 有权具有不同工作和复位电压范围的中继器电路及其方法公开(公告)号：US07595664B1
公开(公告)日：2009-09-29
申请号：US11703323
申请日：2007-02-06
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/01721 , H03K19/00361 , H04L25/242
摘要： A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second subcircuit causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and drive the output to a low state to assist in the falling transition. A third subcircuit resets elements of the first subcircuit. The first subcircuit operates above a first voltage threshold and the third subcircuit operates below the first voltage threshold. A fourth subcircuit resets elements of the second subcircuit. The second subcircuit operates below a second voltage threshold and the fourth subcircuit operates above the second voltage threshold.
摘要翻译： 用于辅助线上信号转换的电路及其方法。 第一分支电路使得耦合到电路的输出的第一晶体管在上升转变期间导通，并将输出驱动到高状态以辅助上升转变。 第二分支电路使得耦合到电路的输出的第二晶体管在下降转变期间导通，并且将输出驱动到低状态以辅助下降转换。 第三个分支电路重置第一个子电路的元素。 第一分支电路工作在第一电压阈值以上，第三子电路工作在第一电压阈值以下。 第四个分支电路复位第二个子电路的元素。 第二分支电路工作在第二电压阈值以下，第四分支电路工作在第二电压阈值以上。
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公开(公告)号：US09911470B2
公开(公告)日：2018-03-06
申请号：US13447037
申请日：2012-04-13
CPC分类号： G11C7/1072 , H03K3/012
摘要： A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.
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公开(公告)号：US20130155783A1
公开(公告)日：2013-06-20
申请号：US13447037
申请日：2012-04-13
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , H03K3/012
摘要： A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.
摘要翻译： 在接收时钟脉冲时立即在数据输出端呈现输入数据的存储器电路包括上游和下游存储器逻辑和选择逻辑。 上游存储器逻辑被配置为在接收时钟脉冲时锁存输入数据。 下游存储器逻辑被配置为存储锁存的输入数据。 选择逻辑被配置为根据上游存储器逻辑是否锁存了输入数据，在输入数据被锁存之前从输入数据导出的暴露逻辑电平以及输入数据之后的锁存输入数据暴露逻辑电平 锁定
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7.发明授权Repeater circuit having different operating and reset voltage ranges, and methods thereof 有权具有不同工作和复位电压范围的中继器电路及其方法公开(公告)号：US07173455B2
公开(公告)日：2007-02-06
申请号：US10879808
申请日：2004-06-28
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/01721 , H03K19/00361 , H04L25/242
摘要： A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second subcircuit causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and drive the output to a low state to assist in the falling transition. A third subcircuit resets elements of the first subcircuit. The first subcircuit operates above a first voltage threshold and the third subcircuit operates below the first voltage threshold. A fourth subcircuit resets elements of the second subcircuit. The second subcircuit operates below a second voltage threshold and the fourth subcircuit operates above the second voltage threshold.
摘要翻译： 用于辅助线上信号转换的电路及其方法。 第一分支电路使得耦合到电路的输出的第一晶体管在上升转变期间导通，并将输出驱动到高状态以辅助上升转变。 第二分支电路使得耦合到电路的输出的第二晶体管在下降转变期间导通，并且将输出驱动到低状态以辅助下降转换。 第三个分支电路重置第一个子电路的元素。 第一分支电路工作在第一电压阈值以上，第三子电路工作在第一电压阈值以下。 第四个分支电路复位第二个子电路的元素。 第二分支电路工作在第二电压阈值以下，第四分支电路工作在第二电压阈值以上。
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