公开(公告)号：US06538488B2

公开(公告)日：2003-03-25

申请号：US09426874

申请日：1999-10-26

申请人： Johnny Q Zhang ,  David B Hollenbeck

发明人： Johnny Q Zhang ,  David B Hollenbeck

IPC分类号： G06F104

CPC分类号： H03K19/018521 ,  G06F1/10

摘要： A clock buffer circuit having a reduced propagation delay therethrough. The clock buffer circuit has a clock input for receiving an initial clock pulse thereto, and a clock output for transmitting a buffered clock pulse therethrough. A first driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from a low voltage level to a high voltage level. A second driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from the high voltage level to the low voltage level. A holder circuit and a first and trigger circuit for the second driver chain are also included.

摘要翻译： 具有减小的传播延迟的时钟缓冲电路。 时钟缓冲电路具有用于接收初始时钟脉冲的时钟输入和用于发送经缓冲的时钟脉冲的时钟输出。 晶体管的第一驱动器链配置与时钟输入和时钟输出耦合，用于将缓冲的时钟脉冲从低电压电平切换到高电压电平。 晶体管的第二驱动器链配置与时钟输入和时钟输出耦合，用于将缓冲的时钟脉冲从高电压电平切换到低电压电平。 还包括用于第二驱动器链的保持器电路和第一触发器电路。

公开(公告)号：US06535989B1

公开(公告)日：2003-03-18

申请号：US09471462

申请日：1999-12-22

申请人： Josef A Dvorak ,  Ricky L Pettit ,  David B Hollenbeck ,  Kent R Townley

发明人： Josef A Dvorak ,  Ricky L Pettit ,  David B Hollenbeck ,  Kent R Townley

IPC分类号： G06F104

CPC分类号： H03K5/1504 ,  G06F1/08 ,  H03L7/0812 ,  H03L7/0996 ,  H03L7/16

摘要： An apparatus for producing one or more clock signals comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A clock signal fed through the plurality of delay elements produces multiple delayed versions of the clock signal. Logic circuitry selects and combines the delayed clock signal versions to produce one or more output clock signals, each having a frequency that is a selected fraction of the input clock signal. An associated method delays the input clock signal N times sequentially for a natural number N. then selects a series of time splices of the delayed clock signals to produce an output clock signal. In some implementations the input clock signal can be referenced to a reference clock signal. The output clock signal frequency can be set to (N/M)×fref, for a natural number M and reference clock signal frequency fref. The apparatus and associated method can flexibly produce a large variety of output clock frequencies and frequency ratios, lock to fref with a dynamic response independent of the output frequency range and can be optimized to a single reference frequency, need not relock to change output frequency, and reduce clock skew.

摘要翻译： 用于产生一个或多个时钟信号的装置包括顺序连接的多个延迟元件和连接到多个延迟元件中的若干个的逻辑电路。 通过多个延迟元件馈送的时钟信号产生时钟信号的多个延迟版本。 逻辑电路选择和组合延迟的时钟信号版本以产生一个或多个输出时钟信号，每个输出时钟信号具有作为输入时钟信号的选定分数的频率。 相关联的方法对自然数N依次延迟输入时钟信号N，然后选择延迟的时钟信号的一系列时间接合以产生输出时钟信号。 在一些实现中，输入时钟信号可以参考参考时钟信号。 对于自然数M和参考时钟信号频率fref，输出时钟信号频率可以设置为（N / M）xfref。 该装置和相关方法可以灵活地产生各种各样的输出时钟频率和频率比，利用独立于输出频率范围的动态响应锁定到fref，并且可以优化到单个参考频率，不需要重新锁定来改变输出频率， 并减少时钟偏差。