公开(公告)号：US20090063940A1

公开(公告)日：2009-03-05

申请号：US11860679

申请日：2007-09-25

申请人： Johnson Yen ,  Ba-Zhong Shen ,  Tak K. Lee

发明人： Johnson Yen ,  Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/41

CPC分类号： H03M13/3955 ,  H03M13/4107 ,  H03M13/4146

摘要： A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within a REX module can be implemented using a radix-4 architecture to increase data throughput. For example, any or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) can be implemented in accordance with the principles of radix-4 decoding processing.

摘要翻译： 提出了一种手段，其中两个网格级可以是彼此同时和并行处理（例如，在单个时钟周期内），从而显着增加数据吞吐量。 REX模块中的任何一个或多个模块可以使用基数4架构来实现，以增加数据吞吐量。 例如，可以根据基数-4解码处理的原理来实现SMU（幸存者存储器单元），PED（路径等效性检测器）和RMU（可靠性测量单元）中的任何一个或多个。

公开(公告)号：US07716564B2

公开(公告)日：2010-05-11

申请号：US11860679

申请日：2007-09-25

申请人： Johnson Yen ,  Ba-Zhong Shen ,  Tak K. Lee

发明人： Johnson Yen ,  Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/03

CPC分类号： H03M13/3955 ,  H03M13/4107 ,  H03M13/4146

摘要： Register exchange network for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within an REX (Register Exchange) module are implemented using a radix-4 architecture to increase data throughput. Any one or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) are implemented in accordance with the principles of radix-4 decoding processing.

摘要翻译： 基数4 SOVA的注册交换网络（软输出维特比算法）。 两个网格级同时并行并行处理（例如，在单个时钟周期内），从而显着增加数据吞吐量。 REX（注册交换）模块中的任何一个或多个模块都使用基数4架构来实现，以增加数据吞吐量。 根据基数4解码处理的原理实现SMU（幸存者存储单元），PED（路径等价检测器）和RMU（可靠性测量单元）中的任何一个或多个。

公开(公告)号：US08341492B2

公开(公告)日：2012-12-25

申请号：US12508459

申请日：2009-07-23

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/1105 ,  H04L1/0068

摘要： Quasi-cyclic LDPC (Low Density Parity Check) code construction is presented that ensures no four cycles therein (e.g., in the bipartite graphs corresponding to the LDPC codes). Each LDPC code has a corresponding LDPC matrix that is composed of square sub-matrices, and based on the size of the sub-matrices of a particular LDPC matrix, then sub-matrix-based cyclic shifting is performed as not only a function of sub-matrix size, but also the row and column indices, to generate CSI (Cyclic Shifted Identity) sub-matrices. When the sub-matrix size is prime (e.g., each sub-matrix being size q×q, where q is a prime number), then it is guaranteed that no four cycles will exist in the resulting bipartite graph corresponding to the LDPC code of that LDPC matrix. When q is a non-prime number, an avoidance set can be used and/or one or more sub-matrices can be made to be an all zero-valued sub-matrix.

摘要翻译： 提出了准循环LDPC（Low Density Parity Check，低密度奇偶校验）码构造，其中不存在四个周期（例如，在对应于LDPC码的二分图中）。 每个LDPC码具有由平方子矩阵组成的对应的LDPC矩阵，并且基于特定LDPC矩阵的子矩阵的大小，然后基于子矩阵的循环移位不仅作为子函数执行 - 矩阵大小，也是行和列索引，以生成CSI（循环移位标识）子矩阵。 当子矩阵大小为素数（例如，每个子矩阵的大小为q×q，其中q为质数）时，则保证在对应于LDPC码的LDPC码的所得到的二分图中不存在四个周期 那个LDPC矩阵。 当q是非素数时，可以使用回避集合和/或可以使一个或多个子矩阵成为全零值子矩阵。

公开(公告)号：US08234551B2

公开(公告)日：2012-07-31

申请号：US12261572

申请日：2008-10-30

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/11

CPC分类号： H03M13/09 ,  H04L1/0057 ,  H04L1/0066

摘要： Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal.

摘要翻译： 用于turbo码块CRC和传输块CRC的单个CRC多项式。 不是采用多个不同的生成多项式来生成用于编码信号内的不同级别的CRC字段，而是针对各种级别使用单个CRC多项式。 通过对CRC编码的各个层使用单个CRC多项式，以最小的硬件要求实现了有效的纠错能力。 这种CRC编码可以在可以在各种各样的通信系统（例如，卫星通信系统，无线通信系统，有线通信系统和光纤通信）中实现的各种通信设备中的任何一种内实现 系统等）。 此外，对于接收信号的CRC的各个层中的每一个，可以在接收机（或收发器）类型通信设备内采用单个CRC校验。

公开(公告)号：US20120192029A1

公开(公告)日：2012-07-26

申请号：US13423381

申请日：2012-03-19

申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1174 ,  H03M13/1151 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/1515 ,  H04L1/0068

摘要： LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

摘要翻译： 具有用CSI（循环移位身份）和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成，并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI（循环移位身份）子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上，另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵（即，其中的所有元素为零“0”）。

公开(公告)号：US08229039B2

公开(公告)日：2012-07-24

申请号：US12273506

申请日：2008-11-18

申请人： Ba-Zhong Shen ,  Sirikiat Lek Ariyavisitakul ,  Mark Kent ,  Tak K. Lee ,  Kelly Brian Cameron

发明人： Ba-Zhong Shen ,  Sirikiat Lek Ariyavisitakul ,  Mark Kent ,  Tak K. Lee ,  Kelly Brian Cameron

IPC分类号： H04L5/12 ,  H04L23/02 ,  H04L27/06 ,  H03M13/00 ,  G06F11/10

CPC分类号： H04L1/1835 ,  H03M13/09 ,  H03M13/2957 ,  H03M13/6306 ,  H04L1/0066 ,  H04L1/1819

摘要： Flexible rate matching. No constraints or restrictions are placed on a sending communication device when effectuating rate matching. The receiving communication device is able to accommodate received transmissions of essentially any size (e.g., up to an entire turbo codeword that includes all systematic bits and all parity bits). The receiving communication device employs a relatively small-sized memory to ensure a lower cost, smaller sized communication device (e.g., handset or user equipment such as a personal wireless communication device). Moreover, incremental redundancy is achieved in which successive transmissions need not include repeated information therein (e.g., a second transmission need not include any repeated information from a first transmission). Only when reaching an end of a block of bits or codeword to be transmitted, and when wrap around at the end of such block of bits or codeword occurs, would any repeat of bits be incurred within a later transmission.

公开(公告)号：US20120063537A1

公开(公告)日：2012-03-15

申请号：US13296348

申请日：2011-11-15

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H04L27/00

CPC分类号： H03M13/2957 ,  H03M13/6356 ,  H04L1/0041 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/0071

摘要： Turbo coding having combined turbo de-padding and rate matching de-padding. An approach is presented by which a singular module is operable to perform both zero bit de-padding and dummy bit de-padding in accordance with turbo encoding. Zero padding can be performed on an input information stream before undergoing turbo encoding. One or more of the 3 outputs from the turbo encoding module (e.g., systematic bits, parity 1 bits, and parity 2 bits) may then undergo dummy bit padding as well. Thereafter, these 3 streams (some or all of which may have undergone dummy bit padding) undergo sub-block interleaving. After all of these operations have taken place, a singular combined de-padding module that can be employed to perform de-padding any zero padded bits and any dummy padded bits from each of the three streams that have undergone the sub-block interleaving.

摘要翻译： Turbo编码具有组合的turbo去填充和速率匹配去填充。 提出了一种方法，通过该方法，单个模块可操作以根据turbo编码执行零比特解除填充和伪比特解除填充。 在进行turbo编码之前，可以对输入信息流执行零填充。 来自turbo编码模块的3个输出中的一个或多个（例如，系统比特，奇偶校验1比特和奇偶校验2比特）然后也可以经历伪比特填充。 此后，这3个流（其中一些或全部可能经历了伪位填充）经历子块交织。 在所有这些操作已经发生之后，可以采用单一组合的去填充模块来执行从填充子块交错的三个流中的每一个中去除任何零填充位和任何虚拟填充位。

公开(公告)号：US08065587B2

公开(公告)日：2011-11-22

申请号：US11811013

申请日：2007-06-07

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2978 ,  H03M13/2775 ,  H03M13/296 ,  H03M13/6516 ,  H03M13/6525 ,  H03M13/6561

摘要： Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size. A novel means is presented by which any desired turbo code block size can be employed when only requiring, in only some instances, a very small number of dummy bits. This approach also is directly adaptable to parallel turbo decoding, in which any desired degree of parallelism can be employed. Alternatively, as few as one turbo decoder can be employed in a fully non-parallel implementation as well. Also, this approach allows for storage of a reduced number of parameters to accommodate a wide variety of interleaves.

摘要翻译： 降低复杂度ARP（几乎规则排列）交错，提供适应任何可能的turbo码块大小的灵活的粒度和并行性。 提出了一种新颖的方法，当仅需要非常少量的虚拟位时，可以采用任何期望的turbo码块大小。 这种方法也可直接适用于平行turbo解码，其中可以采用任何期望的并行度。 或者，也可以在完全非并行实现中使用少至一个turbo解码器。 此外，该方法允许存储少量参数以适应各种各样的交错。

公开(公告)号：US20110107175A1

公开(公告)日：2011-05-05

申请号：US13006029

申请日：2011-01-13

申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1174 ,  H03M13/1151 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/1515 ,  H04L1/0068

摘要： LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

公开(公告)号：US07900127B2

公开(公告)日：2011-03-01

申请号：US12533306

申请日：2009-07-31

申请人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

发明人： Ba-Zhong Shen ,  Hau Thien Tran ,  Tak K. Lee ,  Kelly Brian Cameron

IPC分类号： G06F11/00

CPC分类号： H03M13/1174 ,  H03M13/1151 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/1515 ,  H04L1/0068

摘要： LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).

摘要翻译： 具有用CSI（循环移位身份）和空子矩阵选择性构造的相应奇偶校验矩阵的LDPC（低密度奇偶校验）码。 在通信设备内采用对应于LDPC码的LDPC矩阵来编码和/或解码用于多个通信系统中的任何一个的编码信号。 LDPC矩阵由多个子矩阵组成，并且可以被划分为左手侧矩阵和右手侧矩阵。 右手侧矩阵可以包括其中完全由CSI（循环移位身份）子矩阵组成的两个子矩阵对角线; 这两个子矩阵对角线之一位于中心子矩阵对角线上，另一个位于其左侧。 右侧方矩阵的所有其他子矩阵可以是空子矩阵（即，其中的所有元素为零“0”）。