-
公开(公告)号：US20130275723A1
公开(公告)日：2013-10-17
申请号：US13976230
申请日：2011-11-30
申请人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
发明人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30072 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.
摘要翻译： 在一个实施例中，处理器包括指令解码器，用于接收具有前缀和操作码的第一指令，并且由处理器的指令解码器生成基于基于前缀确定的条件的可执行的第二指令，以及执行 基于基于前缀确定的条件来有条件地执行第二指令的单元。
-
公开(公告)号：US09804852B2
公开(公告)日：2017-10-31
申请号：US13976230
申请日：2011-11-30
申请人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
发明人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30072 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.
-
公开(公告)号：US20130297915A1
公开(公告)日：2013-11-07
申请号：US13976261
申请日：2011-11-14
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.
摘要翻译： 在一个实施例中，处理器包括用于接收和解码具有前缀和操作码的指令的指令解码器，基于操作码执行指令的执行单元和标志修改覆盖逻辑，以防止执行单元修改标志寄存器 的处理器基于指令的前缀。
-
公开(公告)号：US09811338B2
公开(公告)日：2017-11-07
申请号：US13976261
申请日：2011-11-04
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.
-
5.发明授权Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sources 有权使用多个测试源提供OR-test和AND-test功能的易熔指令和逻辑公开(公告)号：US09483266B2
公开(公告)日：2016-11-01
申请号：US13843020
申请日：2013-03-15
CPC分类号： G06F9/3822 , G06F9/30029 , G06F9/30058 , G06F9/30094 , G06F9/3836
摘要： Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag. Some embodiments generate the test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction through a just-in-time compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.
摘要翻译： 易熔指令和逻辑在多个测试源上提供OR测试和与测试功能。 一些实施例包括解码用于执行的测试指令的处理器解码级，指定第一，第二和第三源数据操作数的指令以及操作类型。 执行单元响应于解码的测试指令，根据指定的操作类型在来自第一和第二源数据操作数的数据之间执行一个逻辑操作，并且执行来自第三源数据操作数的数据和 第一个逻辑运算结果设置条件标志。 一些实施例通过将一个逻辑指令与现有技术的测试指令进行融合来动态地产生测试指令。 其他实施例通过即时编译器生成测试指令。 一些实施例还将测试指令与随后的条件分支指令融合，并且根据条件标志的设置来执行分支。
-
公开(公告)号：US08447962B2
公开(公告)日：2013-05-21
申请号：US12644440
申请日：2009-12-22
申请人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3865
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译： 根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。
-
公开(公告)号：US10114651B2
公开(公告)日：2018-10-30
申请号：US15862407
申请日：2018-01-04
申请人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
-
公开(公告)号：US20180129506A1
公开(公告)日：2018-05-10
申请号：US15862407
申请日：2018-01-04
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
CPC分类号： G06F9/3861 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
-
公开(公告)号：US20170192780A1
公开(公告)日：2017-07-06
申请号：US14984078
申请日：2015-12-30
申请人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
发明人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30192
摘要： Embodiments of systems, apparatuses, and method for getting even or odd data elements are described. For example, in some embodiments, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and execution circuitry to execute the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand.
-
公开(公告)号：US20110153983A1
公开(公告)日：2011-06-23
申请号：US12644440
申请日：2009-12-22
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3865
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译： 根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。
-
-
-
-
-
-
-
-
-
搜索结果
172 条记录 (耗时 0.037 秒)
