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公开(公告)号：US20130275723A1
公开(公告)日：2013-10-17
申请号：US13976230
申请日：2011-11-30
申请人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
发明人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30072 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.
摘要翻译： 在一个实施例中，处理器包括指令解码器，用于接收具有前缀和操作码的第一指令，并且由处理器的指令解码器生成基于基于前缀确定的条件的可执行的第二指令，以及执行 基于基于前缀确定的条件来有条件地执行第二指令的单元。
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公开(公告)号：US09804852B2
公开(公告)日：2017-10-31
申请号：US13976230
申请日：2011-11-30
申请人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
发明人： Jonathan D. Combs , Jason W. Brandt , Robert Valentine , Kevin B. Smith , Zia Ansari , Maxim Loktyukhin
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30072 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.
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公开(公告)号：US20130297915A1
公开(公告)日：2013-11-07
申请号：US13976261
申请日：2011-11-14
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.
摘要翻译： 在一个实施例中，处理器包括用于接收和解码具有前缀和操作码的指令的指令解码器，基于操作码执行指令的执行单元和标志修改覆盖逻辑，以防止执行单元修改标志寄存器 的处理器基于指令的前缀。
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公开(公告)号：US09811338B2
公开(公告)日：2017-11-07
申请号：US13976261
申请日：2011-11-04
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.
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5.发明申请公开(公告)号：US20150347267A1
公开(公告)日：2015-12-03
申请号：US14292140
申请日：2014-05-30
CPC分类号： G06F11/348 , G06F11/3466 , G06F2201/86 , G06F2201/88
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to increment upon occurrence of a non-precise event in the processing device. The processing device also includes a precise event based sampling (PEBS) enable control communicably coupled to the performance counter. The processing device also includes a PEBS handler to generate and store a PEBS record including an architectural metadata defining a state of the processing device at a time of generation of the PEBS record. The processing device further includes a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS control and the PEBS handler. The NPEBS module causes the PEBS handler to generate the PEBS record for the non-precise event upon overflow of the performance counter.
摘要翻译： 根据本文公开的实施例，提供了用于监视处理设备的管理非精确事件的性能的系统和方法。 处理装置包括在处理装置中出现非精确事件时增加的性能计数器。 处理设备还包括可通信地耦合到性能计数器的精确的基于事件的采样（PEBS）使能控制。 处理设备还包括PEBS处理器，用于生成和存储包括在生成PEBS记录时定义处理设备的状态的架构元数据的PEBS记录。 处理设备还包括可通信地耦合到PEBS控制和PEBS处理器的非精确事件采样（NPEBS）模块。 NPEBS模块使PEBS处理程序在性能计数器溢出时为非精确事件生成PEBS记录。
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公开(公告)号：US09703566B2
公开(公告)日：2017-07-11
申请号：US13997789
申请日：2011-12-29
IPC分类号： G06F12/00 , G06F9/38 , G06F12/1036
CPC分类号： G06F9/3814 , G06F9/3851 , G06F12/0842 , G06F12/1036 , G06F2212/1024 , G06F2212/657
摘要： In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.
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公开(公告)号：US07552254B1
公开(公告)日：2009-06-23
申请号：US10630286
申请日：2003-07-30
CPC分类号： G06F12/1036 , G06F9/34 , G06F9/3851 , G06F9/3861 , G06F2212/683
摘要： In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space may have entries that include data values associated with the address space identifier.
摘要翻译： 在本发明的一个实施例中，一种装置包括具有不同地址空间的流水线资源，每个对应于不同的地址空间标识符。 每个地址空间可以具有包括与地址空间标识符相关联的数据值的条目。
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公开(公告)号：US20140223141A1
公开(公告)日：2014-08-07
申请号：US13997789
申请日：2011-12-29
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/3851 , G06F12/0842 , G06F12/1036 , G06F2212/1024 , G06F2212/657
摘要： In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.
摘要翻译： 在一些实现中，处理器可以包括诸如翻译后备缓冲器的数据结构，其包括包含具有虚拟地址的第一映射信息和与第一线程相关联的第一上下文的条目。 控制逻辑可以接收对具有虚拟地址的第二映射信息和与第二线程相关联的第二上下文的请求。 控制逻辑可以确定与第二上下文相关联的第二映射信息是否等于数据结构条目中的第一映射信息。 如果第二映射信息等同于第一映射信息，则控制逻辑可以将第二线程与数据结构条目中包含的第一映射信息相关联，以共享第一线程和第二线程之间的条目。
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公开(公告)号：US08447962B2
公开(公告)日：2013-05-21
申请号：US12644440
申请日：2009-12-22
申请人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3865
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译： 根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。
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公开(公告)号：US10114651B2
公开(公告)日：2018-10-30
申请号：US15862407
申请日：2018-01-04
申请人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
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