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公开(公告)号：US20140223141A1
公开(公告)日：2014-08-07
申请号：US13997789
申请日：2011-12-29
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/3851 , G06F12/0842 , G06F12/1036 , G06F2212/1024 , G06F2212/657
摘要： In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.
摘要翻译： 在一些实现中，处理器可以包括诸如翻译后备缓冲器的数据结构，其包括包含具有虚拟地址的第一映射信息和与第一线程相关联的第一上下文的条目。 控制逻辑可以接收对具有虚拟地址的第二映射信息和与第二线程相关联的第二上下文的请求。 控制逻辑可以确定与第二上下文相关联的第二映射信息是否等于数据结构条目中的第一映射信息。 如果第二映射信息等同于第一映射信息，则控制逻辑可以将第二线程与数据结构条目中包含的第一映射信息相关联，以共享第一线程和第二线程之间的条目。
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公开(公告)号：US09811338B2
公开(公告)日：2017-11-07
申请号：US13976261
申请日：2011-11-04
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.
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3.发明申请Aliased Parameter Passing Between Microcode Callers and Microcode Subroutines 审中-公开微代码和微代码子程序之间的别名参数传递公开(公告)号：US20120079248A1
公开(公告)日：2012-03-29
申请号：US12890292
申请日：2010-09-24
CPC分类号： G06F9/384 , G06F9/226 , G06F9/26 , G06F9/30145 , G06F9/3824 , G06F9/4484
摘要： An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the microcode storage. The microcode caller is operable to specify a location of a parameter in the microcode alias location that is indicated by the microinstruction of the microcode subroutine. The apparatus also includes parameter location determination logic that is coupled with the microcode alias locations. The parameter location determination logic is operable, responsive to the microinstruction of the microcode subroutine, to receive the indication of the microcode alias location from the microinstruction and determine the location of the parameter specified in the microcode alias location indicated by the microinstruction.
摘要翻译： 一个方面的装置包括多个微码别名位置和微码存储器。 微代码子程序的微指令存储在微代码存储器中。 微指令具有微代码位置的指示。 微码子程序的微代码调用者也存储在微代码存储器中。 微代码调用者可操作地指定由微代码子程序的微指令指示的微代码别名位置中的参数的位置。 该装置还包括与微码别名位置耦合的参数位置确定逻辑。 参数位置确定逻辑可操作以响应于微代码子程序的微指令，从微指令接收微码别名位置的指示，并确定由微指令指示的微码别名位置中指定的参数的位置。
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公开(公告)号：US09703566B2
公开(公告)日：2017-07-11
申请号：US13997789
申请日：2011-12-29
IPC分类号： G06F12/00 , G06F9/38 , G06F12/1036
CPC分类号： G06F9/3814 , G06F9/3851 , G06F12/0842 , G06F12/1036 , G06F2212/1024 , G06F2212/657
摘要： In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread.
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公开(公告)号：US09367317B2
公开(公告)日：2016-06-14
申请号：US13935363
申请日：2013-07-03
CPC分类号： G06F9/30145 , G06F9/325 , G06F9/381 , G06F9/3822
摘要： A processor includes a microcode storage comprising a plurality of microcode flows and a decode logic coupled to the microcode storage. The decode logic is configured to receive a first instruction, decode the first instruction into an entry point vector to a first microcode flow in the microcode storage, the entry point vector comprising a first indicator specifying a number of clock cycles associated with the first microcode flow, initiate the microcode storage, wherein the microcode storage inserts microinstructions of the first microcode flow into an instruction queue, count clock cycles after initiating the microcode storage, and decode a second instruction without first receiving a return from the microcode storage, wherein the second instruction is decoded at a particular clock cycle based on the number of clock cycles associated with the first microcode flow.
摘要翻译： 处理器包括微代码存储器，其包括多个微码流和耦合到微代码存储器的解码逻辑。 解码逻辑被配置为接收第一指令，将第一指令解码为微代码存储器中的第一微代码流的入口点向量，入口点向量包括指定与第一微代码流相关联的时钟周期数量的第一指示符 启动微代码存储，其中微代码存储将第一微代码流的微指令插入到指令队列中，在启动微代码存储之后对计数时钟周期进行解码，并且在不首先从微代码存储器接收到返回的情况下解码第二指令，其中第二指令 基于与第一微码流相关联的时钟周期的数量在特定时钟周期进行解码。
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公开(公告)号：US20130297915A1
公开(公告)日：2013-11-07
申请号：US13976261
申请日：2011-11-14
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30094 , G06F9/30185
摘要： In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.
摘要翻译： 在一个实施例中，处理器包括用于接收和解码具有前缀和操作码的指令的指令解码器，基于操作码执行指令的执行单元和标志修改覆盖逻辑，以防止执行单元修改标志寄存器 的处理器基于指令的前缀。
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公开(公告)号：US20120166766A1
公开(公告)日：2012-06-28
申请号：US12978471
申请日：2010-12-24
摘要： Methods and apparatus for enhanced microcode address stack pointer manipulation are described. In one embodiment, the stacks are invisible to software. In an embodiment, a microcode instruction pointer (UIP) and a next address to be accessed in a microcode storage unit are generated based on an opcode of a microoperation, a marker, and a UIP stack address. The UIP stack address may be generated based on a signal and an immediate field of the microoperation. Other embodiments are also claimed and disclosed.
摘要翻译： 描述了用于增强的微代码地址堆栈指针操纵的方法和装置。 在一个实施例中，堆栈对于软件是不可见的。 在一个实施例中，微代码指令指针（UIP）和在微代码存储单元中要访问的下一个地址基于微操作的操作码，标记和UIP堆栈地址生成。 可以基于微操作的信号和立即字段来生成UIP堆栈地址。 还要求和公开其它实施例。
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公开(公告)号：US07552254B1
公开(公告)日：2009-06-23
申请号：US10630286
申请日：2003-07-30
CPC分类号： G06F12/1036 , G06F9/34 , G06F9/3851 , G06F9/3861 , G06F2212/683
摘要： In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space may have entries that include data values associated with the address space identifier.
摘要翻译： 在本发明的一个实施例中，一种装置包括具有不同地址空间的流水线资源，每个对应于不同的地址空间标识符。 每个地址空间可以具有包括与地址空间标识符相关联的数据值的条目。
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9.发明申请公开(公告)号：US20150347267A1
公开(公告)日：2015-12-03
申请号：US14292140
申请日：2014-05-30
CPC分类号： G06F11/348 , G06F11/3466 , G06F2201/86 , G06F2201/88
摘要： In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to increment upon occurrence of a non-precise event in the processing device. The processing device also includes a precise event based sampling (PEBS) enable control communicably coupled to the performance counter. The processing device also includes a PEBS handler to generate and store a PEBS record including an architectural metadata defining a state of the processing device at a time of generation of the PEBS record. The processing device further includes a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS control and the PEBS handler. The NPEBS module causes the PEBS handler to generate the PEBS record for the non-precise event upon overflow of the performance counter.
摘要翻译： 根据本文公开的实施例，提供了用于监视处理设备的管理非精确事件的性能的系统和方法。 处理装置包括在处理装置中出现非精确事件时增加的性能计数器。 处理设备还包括可通信地耦合到性能计数器的精确的基于事件的采样（PEBS）使能控制。 处理设备还包括PEBS处理器，用于生成和存储包括在生成PEBS记录时定义处理设备的状态的架构元数据的PEBS记录。 处理设备还包括可通信地耦合到PEBS控制和PEBS处理器的非精确事件采样（NPEBS）模块。 NPEBS模块使PEBS处理程序在性能计数器溢出时为非精确事件生成PEBS记录。
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公开(公告)号：US20150012726A1
公开(公告)日：2015-01-08
申请号：US13935363
申请日：2013-07-03
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/325 , G06F9/381 , G06F9/3822
摘要： A processor includes a microcode storage comprising a plurality of microcode flows and a decode logic coupled to the microcode storage. The decode logic is configured to receive a first instruction, decode the first instruction into an entry point vector to a first microcode flow in the microcode storage, the entry point vector comprising a first indicator specifying a number of clock cycles associated with the first microcode flow, initiate the microcode storage, wherein the microcode storage inserts microinstructions of the first microcode flow into an instruction queue, count clock cycles after initiating the microcode storage, and decode a second instruction without first receiving a return from the microcode storage, wherein the second instruction is decoded at a particular clock cycle based on the number of clock cycles associated with the first microcode flow.
摘要翻译： 处理器包括微代码存储器，其包括多个微码流和耦合到微代码存储器的解码逻辑。 解码逻辑被配置为接收第一指令，将第一指令解码为微代码存储器中的第一微代码流的入口点向量，入口点向量包括指定与第一微代码流相关联的时钟周期数量的第一指示符 启动微代码存储，其中微代码存储将第一微代码流的微指令插入到指令队列中，在启动微代码存储之后对计数时钟周期进行解码，并且在不首先从微代码存储器接收到返回的情况下解码第二指令，其中第二指令 基于与第一微码流相关联的时钟周期的数量在特定时钟周期进行解码。
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