公开(公告)号：US07611964B2

公开(公告)日：2009-11-03

申请号：US12163584

申请日：2008-06-27

申请人： Jong Hye Cho ,  Whee Won Cho ,  Eun Soo Kim

发明人： Jong Hye Cho ,  Whee Won Cho ,  Eun Soo Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L27/11521

摘要： The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer.

摘要翻译： 本发明涉及形成半导体存储器件的隔离层的方法。 根据本发明的半导体存储器件的制造方法，在半导体衬底上形成隧道绝缘层和电荷俘获层。 通过蚀刻电荷陷阱层和隧道绝缘层形成隔离沟槽。 在包括隔离沟槽的整个表面上形成钝化层。 第一绝缘层形成在隔离沟槽的底部。 去除在第一绝缘层的形成过程中被氧化的钝化层的部分。 在包括第一绝缘层的整个表面上形成第二绝缘层。

公开(公告)号：US20090170321A1

公开(公告)日：2009-07-02

申请号：US12137380

申请日：2008-06-11

申请人： Whee Won Cho ,  Jong Hye Cho

发明人： Whee Won Cho ,  Jong Hye Cho

IPC分类号： H01L21/302

CPC分类号： H01L21/76224 ,  H01L27/11521

摘要： A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer.

摘要翻译： 一种形成半导体存储器件的隔离层的方法。 根据本发明的实施例，提供了形成有沟槽的半导体衬底。 在包括沟槽的半导体衬底上形成第一电介质层。 通过执行第一蚀刻工艺以去除第一介电层的一部分，随后进行退火处理来加宽沟槽的开口宽度。 作为蚀刻和退火工艺的结果，在第一介电层中形成的含氟杂质通过执行第二蚀刻工艺而被除去。 在包括第一介电层的半导体衬底之上形成第二电介质层。

公开(公告)号：US08148267B2

公开(公告)日：2012-04-03

申请号：US12137380

申请日：2008-06-11

申请人： Whee Won Cho ,  Jong Hye Cho

发明人： Whee Won Cho ,  Jong Hye Cho

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC分类号： H01L21/76224 ,  H01L27/11521

摘要： A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate including the trenches. An opening width of the trench is widened by performing a first etch process to remove a part of the first dielectric layer, followed by an annealing process. Fluorine-containing impurities formed in the first dielectric layer as a result of the etching and annealing processes are removed by performing a second etch process. A second dielectric layer is formed over the semiconductor substrate including the first dielectric layer.

摘要翻译： 一种形成半导体存储器件的隔离层的方法。 根据本发明的实施例，提供了形成有沟槽的半导体衬底。 在包括沟槽的半导体衬底上形成第一电介质层。 通过执行第一蚀刻工艺以去除第一介电层的一部分，随后进行退火处理来加宽沟槽的开口宽度。 作为蚀刻和退火工艺的结果，在第一介电层中形成的含氟杂质通过执行第二蚀刻工艺而被除去。 在包括第一介电层的半导体衬底之上形成第二电介质层。

公开(公告)号：US20090029522A1

公开(公告)日：2009-01-29

申请号：US11954470

申请日：2007-12-12

申请人： Whee Won Cho ,  Seung Hee Hong ,  Suk Joong Kim ,  Jong Hye Cho

发明人： Whee Won Cho ,  Seung Hee Hong ,  Suk Joong Kim ,  Jong Hye Cho

IPC分类号： H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/31116

摘要： A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first insulating layer, and forming a second insulating layer on the first insulating layer so that the trenches are gap-filled. Thus, trenches can be easily gap-filled with an insulating material.

摘要翻译： 一种形成半导体器件的隔离层的方法，包括在半导体衬底上形成第一绝缘层，该半导体衬底包括在半导体衬底中形成的沟槽，用盐代替第一绝缘层的顶表面，除去盐以扩大第二绝缘层的侧壁之间的空间 第一绝缘层，并且在第一绝缘层上形成第二绝缘层，使得沟槽间隙填充。 因此，沟槽可以容易地用绝缘材料间隙填充。

公开(公告)号：US20080268612A1

公开(公告)日：2008-10-30

申请号：US11962611

申请日：2007-12-21

申请人： Whee Won Cho ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Suk Joong Kim ,  Jong Hye Cho

发明人： Whee Won Cho ,  Cheol Mo Jeong ,  Jung Geun Kim ,  Suk Joong Kim ,  Jong Hye Cho

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： The present invention discloses to a method of forming an isolation layer in a semiconductor device. In particular, the method of forming an isolation layer in a semiconductor device of the present invention comprises the steps of providing a semiconductor substrate on which a trench is formed; forming spacers on side walls of the trench; forming a first insulating layer to fill a portion of the trench such that a deposition rate on the semiconductor substrate which is a bottom surface of the trench and exposed between the spacers is higher than that on a surface of the space; and forming a second insulating layer on the first insulating layer so as to fill the trench with the second insulating layer. An O3-TEOS layer on the exposed semiconductor substrate which is a bottom surface of the trench is grown faster than that on a surface of the spacer formed of an oxide layer or a nitride layer to prevent the O3-TEOS layers grown on the side walls from coming into contact with each other, and so it is possible to inhibit a generation of a seam and to enhance a gap-filling characteristic for the trench.

摘要翻译： 本发明公开了一种在半导体器件中形成隔离层的方法。 特别地，本发明的半导体器件中形成隔离层的方法包括以下步骤：提供其上形成有沟槽的半导体衬底; 在沟槽的侧壁上形成间隔物; 形成第一绝缘层以填充所述沟槽的一部分，使得作为所述沟槽的底表面并暴露在所述间隔物之间​​的所述半导体衬底上的沉积速率高于所述空间的表面上的沉积速率; 以及在所述第一绝缘层上形成第二绝缘层以便用所述第二绝缘层填充所述沟槽。 作为沟槽底面的暴露的半导体衬底上的O 3 -TOS层比由氧化物层或氮化物层形成的间隔物的表面上生长得快，以防止O 在侧壁上生长的3层以上的层彼此接触，因此可以抑制接缝的产生并且增强沟槽的间隙填充特性。

公开(公告)号：US20090004818A1

公开(公告)日：2009-01-01

申请号：US11956865

申请日：2007-12-14

申请人： Seung Woo Shin ,  Eun Soo Kim ,  Suk Joong Kim ,  Jong Hye Cho

发明人： Seung Woo Shin ,  Eun Soo Kim ,  Suk Joong Kim ,  Jong Hye Cho

IPC分类号： H01L21/762

CPC分类号： H01L21/76232 ,  H01L27/11521

摘要： Disclosed herein is a method of fabricating a semiconductor flash memory device, which method avoids and prevents damage to the conductive layer of a floating gate. The disclosed method can prevent a reduction in the charge trap density characteristics and improve the yield of the device.

摘要翻译： 本文公开了一种制造半导体闪速存储器件的方法，该方法避免并防止对浮动栅极的导电层的损坏。 所公开的方法可以防止电荷陷阱密度特性的降低并且提高器件的产量。