公开(公告)号：US06871237B2

公开(公告)日：2005-03-22

申请号：US10418127

申请日：2003-04-18

申请人： Jong Seok Han ,  Yong Seok Choi ,  Sang Man Moh ,  Myung-Joon Kim ,  Kee-Wook Rim

发明人： Jong Seok Han ,  Yong Seok Choi ,  Sang Man Moh ,  Myung-Joon Kim ,  Kee-Wook Rim

IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F13/28

CPC分类号： G06F13/28

摘要： The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance. The data transfer protocol control system with a host bus interface includes a transmitting/receiving command DMA for instructing the command DMA request buffer to read and write command message data, a transmitting data DMA for instructing the transmitting data DMA request buffer to read the command message data, a receiving data DMA for instructing the receiving data DMA request buffer to write the command message data and a data transfer protocol control device for putting read information, write information and message data on a host bus, receiving message data and a transfer response signal and delivering the message data through the response buffer of the corresponding DMA.

摘要翻译： 本发明是一种具有主机总线接口的数据传输协议控制系统，其包括发送/接收命令DMA，发送数据DMA和用于通过主机总线接口控制数据传输协议的接收数据DMA，考虑特性，使用频率，同时 命令DMA和数据DMA的处理功能。 主机接口总线被有效地使用，总线使用率正确分配，以适当地支持传输流程，并提高整个系统性能。 具有主机总线接口的数据传输协议控制系统包括用于指令DMA请求缓冲器读取和写入命令消息数据的发送/接收命令DMA，用于指示发送数据DMA请求缓冲器读取命令消息的发送数据DMA 数据，用于指示接收数据DMA请求缓冲器写入命令消息数据的接收数据DMA和用于将读信息，写信息和消息数据放在主机总线上的数据传输协议控制装置，接收消息数据和传送响应信号 并通过相应DMA的响应缓冲区传送消息数据。

公开(公告)号：US06853588B2

公开(公告)日：2005-02-08

申请号：US10631763

申请日：2003-08-01

申请人： Youngwoo Kim ,  Jae Sung Lee ,  Kyoung Park ,  Sang Man Moh ,  Yong Youn Kim ,  Myung-Joon Kim ,  Kee-Wook Rim

发明人： Youngwoo Kim ,  Jae Sung Lee ,  Kyoung Park ,  Sang Man Moh ,  Yong Youn Kim ,  Myung-Joon Kim ,  Kee-Wook Rim

IPC分类号： G11C7/00 ,  G11C8/04 ,  G11C16/04

CPC分类号： G11C8/04

摘要： In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N>1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n>1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.

摘要翻译： 在使用标准单元库存储器的先进先出存储器电路中，存储块包括N个存储器（N> 1）。 读指针指定N个存储器的读地址。 写指针指定N个存储器的写地址。 存储器控制器基于读/写地址从N个存储器中选择一个，通过将时钟信号递减n（n = N，n> 1）来生成n个读/写时钟信号，并发送n个 对N个存储器具有1 / n个周期差的读/写时钟信号，从而输入/输出数据。

公开(公告)号：US6055599A

公开(公告)日：2000-04-25

申请号：US143787

申请日：1998-08-31

申请人： Jong-Seok Han ,  Kyoung Park ,  Won-Sae Sim ,  Woo-Jong Hahn ,  Kee-Wook Rim

发明人： Jong-Seok Han ,  Kyoung Park ,  Won-Sae Sim ,  Woo-Jong Hahn ,  Kee-Wook Rim

IPC分类号： G06F15/173 ,  G06F13/00

CPC分类号： G06F15/17393

摘要： The present invention relates to a hierarchical crossbar inter-connection network for a cluster-based parallel processing computer. A crossbar network is composed of the "n" number of crossbar switches which is byte sliced, eight links for connecting eight nodes, and two links for connecting other clusters. In addition, one low-level cluster is formed by connecting a maximum of eight processing nodes between the two crossbar networks, and one high-level cluster is formed with a maximum of eight low-level clusters and the four crossbar networks. Moreover, one next high-level clusters formed with a maximum of eight high-level clusters and the eight crossbar networks for scalability.

摘要翻译： 本发明涉及一种用于基于群集的并行处理计算机的层级交叉连接网络。 交叉网络由“n”个字节切换的交叉开关组成，用于连接八个节点的八个链路和用于连接其他集群的两个链路组成。 此外，通过在两个交叉网络之间连接最多八个处理节点来形成一个低级集群，并且一个高级集群形成有最多八个低级集群和四个交叉网络。 此外，一个下一个高级别集群最多可组成八个高级集群，八个交叉网络可扩展。

公开(公告)号：US5964895A

公开(公告)日：1999-10-12

申请号：US866801

申请日：1997-05-30

申请人： Jin-Pyo Kim ,  Joong-Bae Kim ,  Yong-Yun Kim ,  Kee-Wook Rim

发明人： Jin-Pyo Kim ,  Joong-Bae Kim ,  Yong-Yun Kim ,  Kee-Wook Rim

IPC分类号： G06F12/00 ,  G06F11/10 ,  G06F13/00

CPC分类号： G06F11/1076 ,  G06F2211/1009

摘要： A VRAM-based parity engine for use in a disk array controller is disclosed, in which the parity arithmetic operation is carried out in a fast and effective manner, thereby improving the performance of the RAID system. Particularly, the parity data arithmetic operation is not resorted to a processor, but to a VRAM, thereby realizing a high speed operation. In the disk array controller, a VRAM (video RAM) is used, in such a manner that the reading, updating and writing are made to be overlapped during the arithmetic operation, thereby promoting the speed of the arithmetic. Therefore, a relatively large capacity memory can be formed compared with the conventional SRAM, and therefore, a temporary buffer memory within the parity engine is used as a parity cache, thereby doubling the performance.

摘要翻译： 公开了一种用于磁盘阵列控制器的基于VRAM的奇偶校验引擎，其中以快速有效的方式执行奇偶运算操作，从而提高RAID系统的性能。 特别地，奇偶校验数据运算不是处理器，而是VRAM，从而实现高速操作。 在磁盘阵列控制器中，使用VRAM（视频RAM），使得在算术运算期间读取，更新和写入被重叠，从而提高算术速度。 因此，与常规SRAM相比，可以形成相对大的容量存储器，因此，奇偶校验引擎内的临时缓冲存储器被用作奇偶校验高速缓存，从而使性能增加一倍。