公开(公告)号：US06871237B2

公开(公告)日：2005-03-22

申请号：US10418127

申请日：2003-04-18

申请人： Jong Seok Han ,  Yong Seok Choi ,  Sang Man Moh ,  Myung-Joon Kim ,  Kee-Wook Rim

发明人： Jong Seok Han ,  Yong Seok Choi ,  Sang Man Moh ,  Myung-Joon Kim ,  Kee-Wook Rim

IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F13/28

CPC分类号： G06F13/28

摘要： The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance. The data transfer protocol control system with a host bus interface includes a transmitting/receiving command DMA for instructing the command DMA request buffer to read and write command message data, a transmitting data DMA for instructing the transmitting data DMA request buffer to read the command message data, a receiving data DMA for instructing the receiving data DMA request buffer to write the command message data and a data transfer protocol control device for putting read information, write information and message data on a host bus, receiving message data and a transfer response signal and delivering the message data through the response buffer of the corresponding DMA.

摘要翻译： 本发明是一种具有主机总线接口的数据传输协议控制系统，其包括发送/接收命令DMA，发送数据DMA和用于通过主机总线接口控制数据传输协议的接收数据DMA，考虑特性，使用频率，同时 命令DMA和数据DMA的处理功能。 主机接口总线被有效地使用，总线使用率正确分配，以适当地支持传输流程，并提高整个系统性能。 具有主机总线接口的数据传输协议控制系统包括用于指令DMA请求缓冲器读取和写入命令消息数据的发送/接收命令DMA，用于指示发送数据DMA请求缓冲器读取命令消息的发送数据DMA 数据，用于指示接收数据DMA请求缓冲器写入命令消息数据的接收数据DMA和用于将读信息，写信息和消息数据放在主机总线上的数据传输协议控制装置，接收消息数据和传送响应信号 并通过相应DMA的响应缓冲区传送消息数据。

公开(公告)号：US06505289B1

公开(公告)日：2003-01-07

申请号：US09475049

申请日：1999-12-30

申请人： Jong Seok Han ,  Sang Man Moh ,  Woo Jong Hahn ,  Suk Han Yoon

发明人： Jong Seok Han ,  Sang Man Moh ,  Woo Jong Hahn ,  Suk Han Yoon

IPC分类号： G06F1300

CPC分类号： G06F15/17337

摘要： The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2n (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X+ direction, X− direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y+ direction, Y− direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z+ direction, Z− direction.

摘要翻译： 节点连接装置技术领域本发明涉及节点连接装置。 3链节点互连设备和使用该链路节点的并行处理设备可以自由地确定扩展节点，只使用固定的三个连接链路，由于容易划分成2n（n> 1）个节点，因此适合正常的封装方法。 这些装置包括以下节点。 第一个节点分别连接到其他节点的三个链路。 第二节点有三个链路，一个链路连接到第一个节点，另外两个链路负责连接X +方向，X方向。 第三节点有三个链路，一个链路连接到第一个节点，另外两个链路负责Y +方向，Y方向的连接。 第四个节点有三个链路，一个链路连接到第一个节点，另外两个链路负责Z +方向，Z方向的连接。

公开(公告)号：US06415361B1

公开(公告)日：2002-07-02

申请号：US09487348

申请日：2000-01-19

申请人： Sang Man Moh ,  Jong Seok Han ,  An Do Ki ,  Woo Jong Hahn ,  Suk Han Yoon ,  Gil Rok Oh

发明人： Sang Man Moh ,  Jong Seok Han ,  An Do Ki ,  Woo Jong Hahn ,  Suk Han Yoon ,  Gil Rok Oh

IPC分类号： G06F1200

CPC分类号： G06F12/0828 ,  G06F2212/2542

摘要： An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

摘要翻译： 一种用于控制位于节点总线和互连网络之间以执行高速缓存一致性协议的计算节点中的高速缓存的装置包括：用于与节点总线接口的节点总线接口; 用于与互连网络对接的互连网络接口; 用于控制高速缓存以执行高速缓存一致性协议的高速缓存控制逻辑装置; 耦合在所述节点总线接口和所述高速缓存控制逻辑装置之间的总线端双端口事务缓冲器，用于缓冲从计算节点中包含的本地处理器请求和应答的事务; 以及耦合在所述互连网络接口和所述高速缓存控制逻辑之间的网络侧双端口事务缓冲器，用于缓存从耦合到互连网络的另一个计算节点中包含的远程处理器请求和回复的事务。