公开(公告)号：US07671632B2

公开(公告)日：2010-03-02

申请号：US11645605

申请日：2006-12-27

申请人： Jong-hoon Kim ,  Young-chan Jang ,  Jae-jun Lee ,  Kwang-soo Park

发明人： Jong-hoon Kim ,  Young-chan Jang ,  Jae-jun Lee ,  Kwang-soo Park

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H04L25/0272

摘要： A transmission system and method may be provided. The transmission system may transmit 2-bit data for each transmission line set and each transmission line set may include first, second and/or third transmission lines arranged in order. The first, second and/or third transmission lines may respectively transmit first, second and/or third signals each having one of first, second and/or third values such that a combination of a first electric field between the first and second transmission lines and a second electric field between the second and third transmission lines may be made depending on a logic state of the 2-bit data. The transmission system may transmit differential signals using a smaller number of transmission lines and the transmission system may transmit a larger number of signals in the same circuit area.

摘要翻译： 可以提供传输系统和方法。 传输系统可以传送每个传输线路组的2位数据，并且每个传输线路组可以包括按顺序排列的第一，第二和/或第三传输线。 第一，第二和/或第三传输线可以分别发送分别具有第一，第二和/或第三值之一的第一，第二和/或第三信号，使得第一和第二传输线之间的第一电场的组合和 第二和第三传输线之间的第二电场可以根据2位数据的逻辑状态来进行。 传输系统可以使用较少数量的传输线来发送差分信号，并且传输系统可以在相同的电路区域中发送更多数量的信号。

公开(公告)号：US20070146175A1

公开(公告)日：2007-06-28

申请号：US11645605

申请日：2006-12-27

申请人： Jong-hoon Kim ,  Young-chan Jang ,  Jae-Jun Lee ,  Kwang-soo Park

发明人： Jong-hoon Kim ,  Young-chan Jang ,  Jae-Jun Lee ,  Kwang-soo Park

IPC分类号： H03M7/34

CPC分类号： H04L25/0272

摘要： A transmission system and method may be provided. The transmission system may transmit 2-bit data for each transmission line set and each transmission line set may include first, second and/or third transmission lines arranged in order. The first, second and/or third transmission lines may respectively transmit first, second and/or third signals each having one of first, second and/or third values such that a combination of a first electric field between the first and second transmission lines and a second electric field between the second and third transmission lines may be made depending on a logic state of the 2-bit data. The transmission system may transmit differential signals using a smaller number of transmission lines and the transmission system may transmit a larger number of signals in the same circuit area.

摘要翻译： 可以提供传输系统和方法。 传输系统可以传送每个传输线路组的2位数据，并且每个传输线路组可以包括按顺序排列的第一，第二和/或第三传输线。 第一，第二和/或第三传输线可以分别发送分别具有第一，第二和/或第三值之一的第一，第二和/或第三信号，使得第一和第二传输线之间的第一电场的组合和 第二和第三传输线之间的第二电场可以根据2位数据的逻辑状态来进行。 传输系统可以使用较少数量的传输线来传输差分信号，并且传输系统可以在相同的电路区域中发送更多数量的信号。

公开(公告)号：US07821317B2

公开(公告)日：2010-10-26

申请号：US12137595

申请日：2008-06-12

申请人： Young-chan Jang

发明人： Young-chan Jang

IPC分类号： H03K3/00

CPC分类号： H03K5/133 ,  G06F1/08 ,  H03K5/15026 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/0812

摘要： A clock generating apparatus includes a clock generator and a controllable delay line. The clock generator receives an external clock signal and generates multiple clock signals having different phases by delaying the external clock signal. The controllable delay line receives one of the multiple clock signals as a first clock signal and delays the first clock signal by a first interval in response to an externally applied control signal. The delayed first clock signal is input to the clock generator.

摘要翻译： 时钟发生装置包括时钟发生器和可控延时线。 时钟发生器通过延迟外部时钟信号来接收外部时钟信号并产生具有不同相位的多个时钟信号。 可控延迟线接收多个时钟信号中的一个作为第一时钟信号，并且响应于外部施加的控制信号而延迟第一时钟信号第一间隔。 延迟的第一时钟信号被输入到时钟发生器。

公开(公告)号：US20070120582A1

公开(公告)日：2007-05-31

申请号：US11599212

申请日：2006-11-14

申请人： Hoe-ju Chung ,  Young-chan Jang

发明人： Hoe-ju Chung ,  Young-chan Jang

IPC分类号： H03B1/00

CPC分类号： H03K19/01707 ,  H03K17/6871

摘要： An output driver includes a pull-up unit including a pull-up element and a first inductive peaking element connected in series between a first voltage and an output node and a pull-down unit including a pull-down element and a second inductive peaking element connected in series between a second voltage and the output node. The pull-up and pull-down elements receive an input data signal and adjust a voltage level of the output node, and the first and second inductive peaking elements perform an inductive peaking operation when the input data signal transitions.

摘要翻译： 输出驱动器包括上拉单元，其包括上拉元件和串联连接在第一电压和输出节点之间的第一感应峰值元件和下拉单元，该下拉单元包括下拉元件和第二感应峰值元件 串联连接在第二电压和输出节点之间。 上拉和下拉元件接收输入数据信号并调节输出节点的电压电平，并且当输入数据信号转换时，第一和第二感应峰值元件执行感应峰化操作。

公开(公告)号：US20090122904A1

公开(公告)日：2009-05-14

申请号：US12230578

申请日：2008-09-02

申请人： Young-chan Jang ,  Hoe-ju Chung

发明人： Young-chan Jang ,  Hoe-ju Chung

IPC分类号： H04L25/49

CPC分类号： H04L25/4917 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/062

摘要： In one embodiment, the apparatus includes a driver circuit configured such that for each symbol in a set of possible symbols, the driver circuit generates at least one data signal at an associated voltage level. Here, adjacent voltage levels defme an associated voltage interval, and the driver circuit is configured to generate the voltage levels such that a central voltage interval is less than at least one of the voltage intervals adjacent to the central voltage interval.

摘要翻译： 在一个实施例中，该装置包括驱动器电路，其被配置为使得对于一组可能符号中的每个符号，驱动器电路在相关联的电压电平产生至少一个数据信号。 这里，相邻电压电平限定相关联的电压间隔，并且驱动器电路被配置为产生电压电平，使得中心电压间隔小于与中心电压间隔相邻的电压间隔中的至少一个。

公开(公告)号：US07463073B2

公开(公告)日：2008-12-09

申请号：US11599212

申请日：2006-11-14

申请人： Hoe-ju Chung ,  Young-chan Jang

发明人： Hoe-ju Chung ,  Young-chan Jang

IPC分类号： H03B1/00

CPC分类号： H03K19/01707 ,  H03K17/6871

摘要： An output driver includes a pull-up unit including a pull-up element and a first inductive peaking element connected in series between a first voltage and an output node and a pull-down unit including a pull-down element and a second inductive peaking element connected in series between a second voltage and the output node. The pull-up and pull-down elements receive an input data signal and adjust a voltage level of the output node, and the first and second inductive peaking elements perform an inductive peaking operation when the input data signal transitions.

摘要翻译： 输出驱动器包括上拉单元，其包括上拉元件和串联连接在第一电压和输出节点之间的第一感应峰值元件和下拉单元，该下拉单元包括下拉元件和第二感应峰值元件 串联连接在第二电压和输出节点之间。 上拉和下拉元件接收输入数据信号并调节输出节点的电压电平，并且当输入数据信号转换时，第一和第二感应峰值元件执行感应峰化操作。

公开(公告)号：US08457186B2

公开(公告)日：2013-06-04

申请号：US13479886

申请日：2012-05-24

申请人： Young-chan Jang

发明人： Young-chan Jang

IPC分类号： H04B3/46 ,  H04B17/00 ,  H04Q1/20

CPC分类号： H04L25/03885 ,  H04L7/0054

摘要： In the example embodiments, test signals sent from a transmitting system are received at a receiving system. The receiving system generates a determination signal indicating, in one embodiment, whether received signals have a desired relationship with respect to a clock signal at the receiving system. Timing of the clock signal or timing for transmitting signals may be adjusted based on the determination. In another embodiment, the receiving system generates a determination signal indicating whether the pulse width of a lone pulse signal equals a desired time interval. Equalization or pre-emphasis is controlled based on the determination signal.

公开(公告)号：US08213490B2

公开(公告)日：2012-07-03

申请号：US12216557

申请日：2008-07-08

申请人： Young-chan Jang

发明人： Young-chan Jang

IPC分类号： H04B3/46 ,  H04B17/00 ,  H04Q1/20

CPC分类号： H04L25/03885 ,  H04L7/0054

摘要： In the example embodiments, test signals sent from a transmitting system are received at a receiving system. The receiving system generates a determination signal indicating, in one embodiment, whether received signals have a desired relationship with respect to a clock signal at the receiving system. Timing of the clock signal or timing for transmitting signals may be adjusted based on the determination. In another embodiment, the receiving system generates a determination signal indicating whether the pulse width of a lone pulse signal equals a desired time interval. Equalization or pre-emphasis is controlled based on the determination signal.

摘要翻译： 在示例实施例中，从发送系统发送的测试信号在接收系统处被接收。 在一个实施例中，接收系统产生一个确定信号，指示在接收系统中接收到的信号是否与时钟信号有期望的关系。 可以基于该确定来调整用于发送信号的时钟信号或定时的定时。 在另一个实施例中，接收系统产生指示单个脉冲信号的脉冲宽度等于所需时间间隔的确定信号。 基于确定信号来控制均衡或预加重。

公开(公告)号：US07952384B2

公开(公告)日：2011-05-31

申请号：US12637002

申请日：2009-12-14

申请人： Young-chan Jang

发明人： Young-chan Jang

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0002

摘要： A semiconductor device transmitting a plurality of data using a multilevel signal includes a parity bit control unit generating a parity bit that varies with a number of data in which a most significant bit (MSB) and least significant bit (LSB) are different. A data conversion unit either inversely outputs the MSB or the LSB, or outputs the data without a change in response to the parity bit. Transmission units transmit data provided by the data conversion unit using the multilevel signal.

摘要翻译： 使用多电平信号发送多个数据的半导体器件包括奇偶校验位控制单元，其产生随着最高有效位（MSB）和最低有效位（LSB）不同的数据数量而变化的奇偶校验位。 数据转换单元反向输出MSB或LSB，或者输出数据而不改变响应奇偶校验位。 传输单元使用多级信号发送由数据转换单元提供的数据。

公开(公告)号：US20090110040A1

公开(公告)日：2009-04-30

申请号：US12216557

申请日：2008-07-08

申请人： Young-chan Jang

发明人： Young-chan Jang

IPC分类号： H04B17/00 ,  H04L27/00

CPC分类号： H04L25/03885 ,  H04L7/0054

摘要： In the example embodiments, test signals sent from a transmitting system are received at a receiving system. The receiving system generates a determination signal indicating, in one embodiment, whether received signals have a desired relationship with respect to a clock signal at the receiving system. Timing of the clock signal or timing for transmitting signals may be adjusted based on the determination. In another embodiment, the receiving system generates a determination signal indicating whether the pulse width of a lone pulse signal equals a desired time interval. Equalization or pre-emphasis is controlled based on the determination signal.

摘要翻译： 在示例实施例中，从发送系统发送的测试信号在接收系统处被接收。 在一个实施例中，接收系统产生一个确定信号，指示在接收系统中接收到的信号是否与时钟信号有期望的关系。 可以基于该确定来调整用于发送信号的时钟信号或定时的定时。 在另一个实施例中，接收系统产生指示单个脉冲信号的脉冲宽度等于所需时间间隔的确定信号。 基于确定信号来控制均衡或预加重。