公开(公告)号：US20130083612A1

公开(公告)日：2013-04-04

申请号：US13601725

申请日：2012-08-31

申请人： Jong-pil SON ,  Chul-woo PARK

发明人： Jong-pil SON ,  Chul-woo PARK

IPC分类号： G11C29/00

CPC分类号： G11C29/808 ,  G11C29/4401 ,  G11C2029/4402

摘要： A memory device includes a repair circuit including a fail bit location information table configured to store row and column addresses of a defective cell in a normal area of a memory cell array. The repair circuit also includes a row address comparison unit configured to compare the row address of the defective cell with a row address of a first access cell received from the outside, and to output a first row match signal when the defective cell's row address matches the row address of the first access cell, and a column address comparison unit configured to compare the column address of the defective cell with a column address of the first access cell received from the outside, and to output a first column address replacement signal if the column address of the defective cell is the same as the column address of the first access cell.

摘要翻译： 存储器件包括修复电路，该修复电路包括故障位位置信息表，其被配置为存储存储单元阵列的正常区域中的有缺陷单元的行和列地址。 修复电路还包括行地址比较单元，其被配置为将缺陷单元的行地址与从外部接收的第一存取单元的行地址进行比较，并且当缺陷单元的行地址匹配时，输出第一行匹配信号 第一接入小区的行地址，以及列地址比较单元，被配置为将缺陷小区的列地址与从外部接收的第一接入小区的列地址进行比较，并且如果列 故障小区的地址与第一接入小区的列地址相同。

公开(公告)号：US20160077940A1

公开(公告)日：2016-03-17

申请号：US14683705

申请日：2015-04-10

申请人： Jong-pil SON ,  Chul-woo PARK ,  Su-a KIM

发明人： Jong-pil SON ,  Chul-woo PARK ,  Su-a KIM

IPC分类号： G06F11/20

CPC分类号： G06F11/2094 ,  G06F11/1048 ,  G06F2201/85 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/4402

摘要： The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

摘要翻译： 存储器件包括存储器阵列，控制逻辑和恢复电路。 存储器阵列具有被配置为存储数据的第一区域，被配置为存储故障小区信息的一部分的第二区域以及被配置为存储恢复信息的第三区域。 故障小区信息识别第一区域中的故障小区，并且恢复信息用于恢复存储在所识别的故障小区中的数据。 控制逻辑被配置为存储故障小区信息，将故障小区信息的一部分传送到存储器阵列的第二区域，并且基于访问请求中的地址信息确定是否执行恢复操作，并且部分 存储在第二区域中的故障小区信息。 访问请求是访问第一个区域的请求。 恢复电路被配置为执行恢复操作。

公开(公告)号：US20130088912A1

公开(公告)日：2013-04-11

申请号：US13535583

申请日：2012-06-28

申请人： Jong-pil SON ,  Dong-min KIM

发明人： Jong-pil SON ,  Dong-min KIM

IPC分类号： G11C7/06 ,  G11C11/24 ,  G11C7/00

CPC分类号： G11C7/08 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

摘要： A semiconductor memory device includes a first bit line to which a first memory cell is connected, and a second bit line to which a second memory cell is connected, the second bit line being complementary to the first bit line, a sense amplifier that includes a first transistor and a second transistor connected in series between the first bit line and the second bit line, the sense amplifier including a first node between the first transistor and the second transistor, a gate of the first transistor being connected to the second bit line, and a gate of the second transistor being connected to the first bit line, and a voltage providing unit that provides a first voltage to the first node during presensing, and provides a second voltage, different from the first voltage, to the first node during main sensing.

摘要翻译： 半导体存储器件包括第一存储器单元连接到的第一位线和连接第二存储器单元的第二位线，第二位线与第一位线互补，读出放大器包括： 第一晶体管和第二晶体管串联连接在第一位线和第二位线之间，读出放大器包括第一晶体管和第二晶体管之间的第一节点，第一晶体管的栅极连接到第二位线， 并且所述第二晶体管的栅极连接到所述第一位线，以及电压提供单元，其在预定期间向所述第一节点提供第一电压，并且在所述第一节点期间在所述第一节点期间向所述第一节点提供与所述第一电压不同的第二电压 感应。