公开(公告)号：US20100174959A1

公开(公告)日：2010-07-08

申请号：US12652768

申请日：2010-01-06

申请人： Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

发明人： Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

IPC分类号： H03M13/03 ,  G06F11/10

CPC分类号： H03M13/1111 ,  H03M13/1108 ,  H03M13/3707 ,  H03M13/451 ,  H03M13/458 ,  H04L1/0045 ,  H04L1/0057

摘要： A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.

摘要翻译： 解码方法包括当解码第一解码方法失败时执行第一解码方法并执行第二解码方法。 第一解码方法包括使用接收数据的概率值来更新多个可变节点和多个校验节点。 第二解码方法包括从多个可变节点中选择至少一个变量节点; 校正在所选择的至少一个可变节点中接收的数据的概率值; 使用校正的概率值更新变量节点和校验节点; 以及确定所述第二解码方法的解码是否成功。

公开(公告)号：US08397116B2

公开(公告)日：2013-03-12

申请号：US12652768

申请日：2010-01-06

申请人： Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

发明人： Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

IPC分类号： H03M13/00

CPC分类号： H03M13/1111 ,  H03M13/1108 ,  H03M13/3707 ,  H03M13/451 ,  H03M13/458 ,  H04L1/0045 ,  H04L1/0057

摘要： A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.

摘要翻译： 解码方法包括当解码第一解码方法失败时执行第一解码方法并执行第二解码方法。 第一解码方法包括使用接收数据的概率值来更新多个可变节点和多个校验节点。 第二解码方法包括从多个可变节点中选择至少一个变量节点; 校正在所选择的至少一个可变节点中接收的数据的概率值; 使用校正的概率值更新变量节点和校验节点; 以及确定所述第二解码方法的解码是否成功。

公开(公告)号：US08339846B2

公开(公告)日：2012-12-25

申请号：US12856698

申请日：2010-08-16

申请人： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

发明人： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642

摘要： The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

摘要翻译： 闪存器件包括控制逻辑电路和位电平转换逻辑电路。 控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位 读命令。 在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。 位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取 ）位，然后编程或读取其他2N个单元分布。

公开(公告)号：US20110038207A1

公开(公告)日：2011-02-17

申请号：US12856698

申请日：2010-08-16

申请人： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

发明人： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642

摘要： The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

摘要翻译： 闪存器件包括控制逻辑电路和位电平转换逻辑电路。 控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位 读命令。 在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。 位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取 ）位，然后编程或读取其他2N个单元分布。

公开(公告)号：US07330264B2

公开(公告)日：2008-02-12

申请号：US11071819

申请日：2005-03-03

申请人： Jang-seok Ma ,  Fu Wang ,  In-jae Lee ,  Soo-suk Lee ,  Young-nam Kwon ,  Young-hoon Kim ,  Hui-jun Sim ,  In-ho Lee ,  Young-hwan Lee

发明人： Jang-seok Ma ,  Fu Wang ,  In-jae Lee ,  Soo-suk Lee ,  Young-nam Kwon ,  Young-hoon Kim ,  Hui-jun Sim ,  In-ho Lee ,  Young-hwan Lee

IPC分类号： G01N21/55

CPC分类号： G01N21/648 ,  G01N21/6454

摘要： An optical detection device for biochemically analyzing samples of microfluidic chips such as DNA chips or protein chips is provided. The optical detection device includes a light source for generating excitation light to excite a sample, a detection plate having an optical waveguide with the sample mounted thereon, a linear symmetry lens for shaping the excitation light into a desired shape having a uniform intensity distribution and transmitting it to the detection plate, and a detector for detecting radiation from the sample.

摘要翻译： 提供了用于生物化学分析诸如DNA芯片或蛋白质芯片之类的微流体芯片的样品的光学检测装置。 光学检测装置包括用于产生激发光以激发样品的光源，具有安装有样品的光波导的检测板，用于将激发光成形为具有均匀强度分布和传输的所需形状的线性对称透镜 检测板，以及用于检测来自样品的辐射的检测器。

公开(公告)号：US20050195394A1

公开(公告)日：2005-09-08

申请号：US11071819

申请日：2005-03-03

申请人： Jang-seok Ma ,  Fu Wang ,  In-jae Lee ,  Soo-suk Lee ,  Young-nam Kwon ,  Young-hoon Kim ,  Hui-jun Sim ,  In-ho Lee ,  Young-hwan Lee

发明人： Jang-seok Ma ,  Fu Wang ,  In-jae Lee ,  Soo-suk Lee ,  Young-nam Kwon ,  Young-hoon Kim ,  Hui-jun Sim ,  In-ho Lee ,  Young-hwan Lee

IPC分类号： G01J3/30 ,  G01N21/64

CPC分类号： G01N21/648 ,  G01N21/6454

摘要： An optical detection device for biochemically analyzing samples of microfluidic chips such as DNA chips or protein chips is provided. The optical detection device includes a light source for generating excitation light to excite a sample, a detection plate having an optical waveguide with the sample mounted thereon, a linear symmetry lens for shaping the excitation light into a desired shape having a uniform intensity distribution and transmitting it to the detection plate, and a detector for detecting radiation from the sample.

摘要翻译： 提供了用于生物化学分析诸如DNA芯片或蛋白质芯片之类的微流体芯片的样品的光学检测装置。 光学检测装置包括用于产生激发光以激发样品的光源，具有安装有样品的光波导的检测板，用于将激发光成形为具有均匀强度分布和传输的所需形状的线性对称透镜 检测板，以及用于检测来自样品的辐射的检测器。