公开(公告)号：US20100174959A1

公开(公告)日：2010-07-08

申请号：US12652768

申请日：2010-01-06

申请人： Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

发明人： Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

IPC分类号： H03M13/03 ,  G06F11/10

CPC分类号： H03M13/1111 ,  H03M13/1108 ,  H03M13/3707 ,  H03M13/451 ,  H03M13/458 ,  H04L1/0045 ,  H04L1/0057

摘要： A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.

摘要翻译： 解码方法包括当解码第一解码方法失败时执行第一解码方法并执行第二解码方法。 第一解码方法包括使用接收数据的概率值来更新多个可变节点和多个校验节点。 第二解码方法包括从多个可变节点中选择至少一个变量节点; 校正在所选择的至少一个可变节点中接收的数据的概率值; 使用校正的概率值更新变量节点和校验节点; 以及确定所述第二解码方法的解码是否成功。

公开(公告)号：US08397116B2

公开(公告)日：2013-03-12

申请号：US12652768

申请日：2010-01-06

申请人： Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

发明人： Jong-seon No ,  Beom-kyu Shin ,  Ho-sung Park ,  Yong-june Kim ,  Jae-hong Kim ,  Young-hwan Lee ,  Jun-jin Kong

IPC分类号： H03M13/00

CPC分类号： H03M13/1111 ,  H03M13/1108 ,  H03M13/3707 ,  H03M13/451 ,  H03M13/458 ,  H04L1/0045 ,  H04L1/0057

摘要： A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful.

摘要翻译： 解码方法包括当解码第一解码方法失败时执行第一解码方法并执行第二解码方法。 第一解码方法包括使用接收数据的概率值来更新多个可变节点和多个校验节点。 第二解码方法包括从多个可变节点中选择至少一个变量节点; 校正在所选择的至少一个可变节点中接收的数据的概率值; 使用校正的概率值更新变量节点和校验节点; 以及确定所述第二解码方法的解码是否成功。

公开(公告)号：US20110038207A1

公开(公告)日：2011-02-17

申请号：US12856698

申请日：2010-08-16

申请人： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

发明人： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642

摘要： The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

摘要翻译： 闪存器件包括控制逻辑电路和位电平转换逻辑电路。 控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位 读命令。 在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。 位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取 ）位，然后编程或读取其他2N个单元分布。

公开(公告)号：US08339846B2

公开(公告)日：2012-12-25

申请号：US12856698

申请日：2010-08-16

申请人： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

发明人： Hee-seok Eun ,  Jong-han Kim ,  Jae-hong Kim ,  Dong-hyuk Chae ,  Seung-hwan Song ,  Han-woong Yoo ,  Jun-jin Kong ,  Young-hwan Lee ,  Kyoung-lae Cho ,  Yong-june Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642

摘要： The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through Nth bits of data in a memory cell array of the N-bit MLC flash memory device or reads the first through Nth bits of the data from the memory cell array in response to one of a program command and a read command. The bit level conversion control logic circuit, after the first through Nth bits of the data are completely programmed or read, programs or reads an (N+1)th bit of the data in response to a control signal. The bit level conversion control logic circuit converts voltage levels of voltages, which are used for programming or reading the first through Nth bits of the data, to program or read for 2N cell distributions of 2N+1 cell distributions corresponding to the (N+1)th bit of the data and then programs or reads for other 2N cell distributions.

摘要翻译： 闪存器件包括控制逻辑电路和位电平转换逻辑电路。 控制逻辑电路对N位MLC闪速存储器件的存储单元阵列中的第一至第N位数据进行编程，或响应于程序命令和程序命令之一从存储单元阵列中读取数据的第一至第N位 读命令。 在数据的第一至第N位被完全编程或读取之后，位电平转换控制逻辑电路响应于控制信号编程或读取数据的第（N + 1）位。 位电平转换控制逻辑电路转换用于编程或读取数据的第一至第N位的电压电平，以对与第（N + 1）个对应的2N + 1个单元分布的2N个单元分布进行编程或读取 ）位，然后编程或读取其他2N个单元分布。

公开(公告)号：US06820232B2

公开(公告)日：2004-11-16

申请号：US09905995

申请日：2001-07-17

申请人： Jae-hong Kim ,  Jun-jin Kong ,  Sung-han Choi

发明人： Jae-hong Kim ,  Jun-jin Kong ,  Sung-han Choi

IPC分类号： H03M1300

CPC分类号： H03M13/09

摘要： A device for detecting in a receiver whether any transmission errors have occurred in the received CRC code, in a case that a transmitter transmits the CRC code created by sequencing the parity bits, which are generated using the generator polynomial, in the reverse order and appending them to the message bits. The device comprises a division unit for dividing the message bits by the parity bit generator polynomial to form the remainder, a comparison unit for bitwise comparing the remainder bits with the reverse ordered parity bits, and a decision unit for deciding whether transmission errors have occurred in the CRC code based on the results of the comparison unit. According to the present invention, the transmission errors in the received CRC code are effectively detected, when the CRC code includes the parity bits sequenced in the reverse order, unlike the conventional normal order.

摘要翻译： 在接收到的CRC码中检测出发送错误是否发生的发送装置，在发送方通过使用生成多项式生成的奇偶校验位进行排序创建的CRC码的情况下，以相反的顺序进行检测，并附加 他们到消息位。 该装置包括：分割单元，用于将消息比特除以奇偶校验位生成多项式以形成余数;比较单元，用于将余数比特与反向有序奇偶校验比特进行比较;以及判定单元，用于判定是否发生了传输错误 基于比较单元结果的CRC码。 根据本发明，与传统的正常顺序不同，当CRC码包括以相反顺序排列的奇偶校验位时，有效地检测出接收的CRC码中的传输错误。

公开(公告)号：US07590831B2

公开(公告)日：2009-09-15

申请号：US11514889

申请日：2006-09-05

申请人： Soo-jung Ryu ,  Jeong-wook Kim ,  Suk-jin Kim ,  Hong-Seok Kim ,  Jun-jin Kong

发明人： Soo-jung Ryu ,  Jeong-wook Kim ,  Suk-jin Kim ,  Hong-Seok Kim ,  Jun-jin Kong

IPC分类号： G06F9/44

CPC分类号： G06F9/3836 ,  G06F9/3877 ,  G06F9/3897 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop part, and a central register file which transmits data between the processor core and the loop accelerator. The loop accelerator includes a plurality of processing elements (PEs) each of which performs an operation on each word to execute the program, a configuration memory which stores configuration bits indicating operations, states, etc. of the PEs, and a plurality of context memories, installed in a column or row direction of the PEs, which transmit the configuration bits along a direction toward which the PEs are arrayed. Thus, a connection structure between the configuration memory and the PEs can be simplified to easily modify a structure of the loop accelerator so as to extend the loop accelerator.

摘要翻译： 提供了一种环路加速器和具有环路加速器的数据处理系统。 数据处理系统包括执行程序的循环部分的循环加速器，处理除循环部分之外的程序的剩余部分的处理器核心以及在处理器核心和循环加速器之间传送数据的中央寄存器文件。 环路加速器包括多个处理元件（PE），每个处理元件（PE）对每个字执行操作以执行程序;配置存储器，其存储指示PE的操作，状态等的配置位，以及多个上下文存储器 安装在PE的列或行方向上，其沿着PE排列的方向传送配置位。 因此，可以简化配置存储器和PE之间的连接结构，以容易地修改循环加速器的结构，以便扩展循环加速器。

公开(公告)号：US06799296B2

公开(公告)日：2004-09-28

申请号：US09985122

申请日：2001-11-01

申请人： Jun-jin Kong ,  Sung-han Choi ,  Jae-wook Lee

发明人： Jun-jin Kong ,  Sung-han Choi ,  Jae-wook Lee

IPC分类号： H03M1300

CPC分类号： H03M13/6343 ,  G11B20/10009 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107

摘要： A high speed Viterbi detector for an optical disk system, includes a frequency dividing unit for generating an auxiliary clock at one-third of the main clock frequency, a branch metric calculation unit for calculating each of a plurality of branch metrics, a serial-to-parallel converting unit for outputting each of the branch metrics at the main clock frequency in units of 3 state bits, an addition/comparison/selection unit for adding the branch metrics and previously stored state metrics and for comparing the addition results to select and output the minimum of the addition results as a new state metric, and for outputting a corresponding path selection signal, at the auxiliary clock frequency, a path memory for storing the path selection signal and for outputting parallel data corresponding to the path selection signal, at the auxiliary clock frequency, and a parallel-to-serial converting unit for converting the path memory output into serial data.

摘要翻译： 一种用于光盘系统的高速维特比检测器，包括用于产生主时钟频率三分之一的辅助时钟的分频单元，用于计算多个分支度量中的每一个的分支量度计算单元， 平行转换单元，用于以3个状态位为单位输出主时钟频率的每个分支度量，用于添加分支度量和先前存储的状态度量的加法/比较/选择单元，并用于比较加法结果以选择和输出 将附加结果的最小值作为新的状态度量，并且在辅助时钟频率处输出用于存储路径选择信号并用于输出与路径选择信号相对应的并行数据的路径存储器的相应路径选择信号， 辅助时钟频率以及用于将路径存储器输出转换为串行数据的并行到串行转换单元。

公开(公告)号：US6029268A

公开(公告)日：2000-02-22

申请号：US839

申请日：1997-12-30

申请人： Jun-jin Kong ,  Sung-han Choi

发明人： Jun-jin Kong ,  Sung-han Choi

IPC分类号： H04L29/14 ,  H03M13/23 ,  H03M13/35 ,  H03M13/41 ,  G06F11/10

CPC分类号： H03M13/6569 ,  H03M13/35 ,  H03M13/4107 ,  H03M13/413

摘要： A quality calculator apparatus for Viterbi-decoded data using zero-state metrics. The quality calculator for the Viterbi-decoded data includes: a Viterbi decoder which outputs zero-state metrics of input demodulated data according to the four possible transmission rates of FULL, HALF, QUARTER and 1/8; a register which stores respective zero-state metrics output from the Viterbi decoder; and a quality evaluation unit which reads the zero-state metrics stored in the register to evaluate the Viterbi-decoded data based on the zero-state metrics and which determines the actual transmission rate to be the one among the possible transmission rates which has the least zero-state metrics. The zero-state metrics of the demodulated data input to the Viterbi decoder are used as a quality evaluation parameter so that the quality evaluation can be correctly achieved to avoid errors in determining of the transmission rate, as compared to a quality calculator using a bit error ratio as the quality evaluation parameter.

摘要翻译： 一种使用零状态度量的维特比解码数据的质量计算器装置。 用于维特比解码数据的质量计算器包括：维特比解码器，其根据FULL，HALF，QUARTER和+ E，fra 1/8 + EE的四种可能的传输速率输出输入解调数据的零状态度量; 存储从维特比解码器输出的相应的零状态度量的寄存器; 以及质量评估单元，其读取存储在所述寄存器中的零状态度量，以基于所述零状态量度来评估所述维特比解码数据，并且将所述实际传输速率确定为所述可能传输速率中的最小传输速率 零状态指标。 将输入到维特比解码器的解调数据的零状态量度用作质量评估参数，以便与使用位错误的质量计算器相比，可以正确地实现质量评估以避免确定传输速率的错误 比例作为质量评估参数。

公开(公告)号：US5881075A

公开(公告)日：1999-03-09

申请号：US814828

申请日：1997-03-11

申请人： Jun-jin Kong ,  Yong-woo Park

发明人： Jun-jin Kong ,  Yong-woo Park

IPC分类号： H03M13/23 ,  H03M13/41 ,  G06F11/10

CPC分类号： H03M13/3961 ,  H03M13/4107

摘要： A Viterbi decoder which operates a plurality of states at one time to thereby decode a plurality of channels at an increased speed. The decoder includes a branch metric calculating unit which receives convolutional data and calculates a plurality of branch metrics. A branch metric allocating unit allocates the plurality of branch metrics as even and odd branch metrics. A state metric storing unit stores a current state metric and allocates a plurality of state metrics as even and odd state metrics. First and second add-compare-select (ACS) units perform addition, comparison, and selection on the even branch and state metrics, and select paths having optimum distances. Third and fourth ACS units perform addition, comparison, and selection on the odd branch and state metrics, and select paths having optimum distances. A path tracing logic unit traces the path selection information selected in the first through fourth ACS units, and outputs decoded data. A path storing unit stores a path selection signal generated and selected in the path selection information controller.

摘要翻译： 一种维特比解码器，其一次操作多个状态，从而以增加的速度解码多个信道。 解码器包括分支度量计算单元，其接收卷积数据并计算多个分支度量。 分支度量分配单元将多个分支度量分配为偶数和奇数分支度量。 状态度量存储单元存储当前状态度量，并且将多个状态度量分配为偶数和奇数状态度量。 第一和第二加 - 比选择（ACS）单元对偶分支和状态度量进行加法，比较和选择，并选择具有最佳距离的路径。 第三和第四ACS单元对奇数分支和状态度量执行加法，比较和选择，并选择具有最佳距离的路径。 路径跟踪逻辑单元跟踪在第一至第四ACS单元中选择的路径选择信息，并输出解码数据。 路径存储单元存储在路径选择信息控制器中生成和选择的路径选择信号。

公开(公告)号：US09524208B2

公开(公告)日：2016-12-20

申请号：US14322404

申请日：2014-07-02

申请人： Kyung-Jin Kim ,  Ung-Hwan Kim ,  Jun-jin Kong ,  Nam-Shik Kim

发明人： Kyung-Jin Kim ,  Ung-Hwan Kim ,  Jun-jin Kong ,  Nam-Shik Kim

IPC分类号： G06F11/10 ,  H03M13/11 ,  H03M13/29 ,  H03M13/37 ,  H03M13/41 ,  H03M13/45 ,  H03M13/00 ,  G11C29/52 ,  H03M13/39

CPC分类号： G06F11/1048 ,  G06F11/1012 ,  G06F11/1068 ,  G11C29/52 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/2927 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/3707 ,  H03M13/3738 ,  H03M13/3746 ,  H03M13/3927 ,  H03M13/41 ,  H03M13/45 ,  H03M13/458 ,  H03M13/6513

摘要： A method of operating a memory controller includes; receiving hard decision data and first soft decision data from a non-volatile memory device, performing a first ECC decoding operation using the hard decision data and the first soft decision data: and then determining a second soft decision read voltage or reclaim operation of the non-volatile memory device based on the number of iteration operation of the first ECC (error correction code).

摘要翻译： 操作存储器控制器的方法包括： 从非易失性存储设备接收硬判决数据和第一软判决数据，使用硬判决数据和第一软判决数据执行第一ECC解码操作;然后确定第二软判决读电压或回收非非易失性存储器 基于第一ECC的迭代操作次数（纠错码）的非易失性存储装置。