公开(公告)号：US06507522B2

公开(公告)日：2003-01-14

申请号：US09841917

申请日：2001-04-24

申请人： Joon-Sung Lee ,  Chan-Jo Lee ,  Yun-Heub Song ,  Seung-Keun Lee

发明人： Joon-Sung Lee ,  Chan-Jo Lee ,  Yun-Heub Song ,  Seung-Keun Lee

IPC分类号： G11C1604

CPC分类号： G11C16/3477 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3468

摘要： A method for managing memory cells in a nonvolatile memory, such as a flash memory, includes detecting and intermediately programming fast-erased memory cells. All of the memory cells in a sector can then be erased.

摘要翻译： 用于管理非易失性存储器（诸如闪速存储器）中的存储器单元的方法包括检测和中间编程快速擦除的存储器单元。 然后可以擦除扇区中的所有存储单元。

公开(公告)号：US6015996A

公开(公告)日：2000-01-18

申请号：US906433

申请日：1997-08-05

申请人： Chan-Jo Lee

发明人： Chan-Jo Lee

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L23/48 ,  H01L29/94

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  Y10S257/903

摘要： A static RAM which is a CMOS static RAM having first and second load transistors, first and second driver transistors, and first and second switching transistors in one memory cell includes: a laminated structure of a first polysilicon layer, a silicide layer and a second polysilicon layer, forming the gate regions of the second load and driver transistors in a body; an interconnection layer comprising a laminated structure of the silicide layer and the second polysilicon layer to form a p-n junction between the drain regions of the first load and driver transistors; and one contact for making the gate regions and the interconnection layer in a body by the second polysilicon layer.

摘要翻译： 具有第一和第二负载晶体管的CMOS静态RAM的静态RAM，第一和第二驱动晶体管以及一个存储单元中的第一和第二开关晶体管包括：第一多晶硅层，硅化物层和第二多晶硅层 层，形成体内第二负载和驱动晶体管的栅极区; 包括硅化物层和第二多晶硅层的层叠结构的互连层，以在第一负载和驱动晶体管的漏极区之间形成p-n结; 以及用于通过第二多晶硅层使主体中的栅极区域和互连层形成的一个触点。

公开(公告)号：US6011712A

公开(公告)日：2000-01-04

申请号：US982998

申请日：1997-12-03

申请人： Chan-Jo Lee

发明人： Chan-Jo Lee

IPC分类号： H01L21/74 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： Interconnection structures for integrated circuits include first and second spaced apart active regions in an integrated circuit at a face thereof and a recessed isolation region in the integrated circuit, between the first and second spaced apart active regions and recessed beneath the face. A first conductive layer is included on the recessed isolation region. The first conductive layer extends between the first and second spaced apart active regions beneath the face, and electrically connects the first and second spaced apart active regions beneath the face. Accordingly, high density isolation regions and interconnection regions for the first and second spaced apart active regions are provided. A second conductive layer is preferably included on the face, extending from on the first active region onto the first conductive layer and onto the second active region. The interconnect structures may be formed by forming an isolation region in a face of an integrated circuit substrate, and first and second spaced apart active regions in the integrated circuit substrate at the face. A portion of the isolation region is removed, to form a recessed isolation region. A first conductive layer is formed on the recessed isolation region such that the first and second spaced apart regions and the first conductive layer are electrically interconnected beneath the face. A second conductive layer is formed on the face, extending from on the first active region onto the first conductive layer and onto the second region.

摘要翻译： 用于集成电路的互连结构包括在其一侧的集成电路中的第一和第二间隔的有源区域以及集成电路中的凹陷隔离区域，位于第一和第二间隔开的有源区域之间并且凹陷在面下方。 第一导电层包括在凹陷隔离区域中。 第一导电层在面之下的第一和第二间隔开的有源区之间延伸，并且电连接面下面的第一和第二间隔开的有源区。 因此，提供了用于第一和第二间隔开的有源区域的高密度隔离区域和互连区域。 第二导电层优选包括在表面上，从第一有源区延伸到第一导电层上并延伸到第二有源区上。 互连结构可以通过在集成电路基板的表面形成隔离区域，并且在集成电路基板的表面上形成第一和第二间隔开的有源区域。 去除隔离区域的一部分，以形成凹入的隔离区域。 在凹陷的隔离区域上形成第一导电层，使得第一和第二间隔开的区域和第一导电层在面下电互连。 第二导电层形成在表面上，从第一有源区延伸到第一导电层上并延伸到第二区上。