公开(公告)号：US20200310800A1

公开(公告)日：2020-10-01

申请号：US16366941

申请日：2019-03-27

申请人： Jorge PARRA ,  Dan BAUM ,  Robert CHAPPELL ,  Michael ESPIG ,  Varghese GEORGE ,  Alexander HEINECKE ,  Christopher HUGHES ,  Subramaniam MAIYURAN ,  Elmoustapha OULD-AHMED-VALL ,  Prasoonkumar SURTI ,  Ronen ZOHAR

发明人： Jorge PARRA ,  Dan BAUM ,  Robert CHAPPELL ,  Michael ESPIG ,  Varghese GEORGE ,  Alexander HEINECKE ,  Christopher HUGHES ,  Subramaniam MAIYURAN ,  Elmoustapha OULD-AHMED-VALL ,  Prasoonkumar SURTI ,  Ronen ZOHAR

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/34 ,  G06F17/11

摘要： Methods and apparatus for approximation using polynomial functions are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry is to decode an instruction, where the instruction comprises a first operand specifying an output location and a second operand specifying a plurality of data element values to be computed. The execution circuitry is to execute the decoded instruction. The execution includes to compute a result for each of the plurality of data element values using a polynomial function to approximate a complex function, where the computation uses coefficients stored in a lookup location for the complex function, and where data element values within different data element value ranges use different sets of coefficients. The execution further includes to store results of the computation in the output location.

公开(公告)号：US20190042245A1

公开(公告)日：2019-02-07

申请号：US16146854

申请日：2018-09-28

申请人： Bret TOLL ,  Alexander F. HEINECKE ,  Christopher J. HUGHES ,  Ronen ZOHAR ,  Michael ESPIG ,  Dan BAUM ,  Raanan SADE ,  Robert VALENTINE

发明人： Bret TOLL ,  Alexander F. HEINECKE ,  Christopher J. HUGHES ,  Ronen ZOHAR ,  Michael ESPIG ,  Dan BAUM ,  Raanan SADE ,  Robert VALENTINE

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06

摘要： Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

公开(公告)号：US20240103865A1

公开(公告)日：2024-03-28

申请号：US18193413

申请日：2023-03-30

申请人： Michael ESPIG ,  Mikko BYCKLING ,  Maxim LOKTYUKHIN ,  Dmitry Yurievich BABOKIN ,  Amit GRADSTEIN ,  Deepti AGGARWAL

发明人： Michael ESPIG ,  Mikko BYCKLING ,  Maxim LOKTYUKHIN ,  Dmitry Yurievich BABOKIN ,  Amit GRADSTEIN ,  Deepti AGGARWAL

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/3001 ,  G06F9/30036

摘要： Techniques for using and/or supporting multiplication with add and/or subtract instructions with an intermediate (after multiplication) round are described. In some examples, an instruction at least having one or more fields for an opcode and location information for three packed data source operands, wherein the opcode is to indicate execution circuitry is to perform, per packed data element position, a multiplication, a round, addition and/or subtraction, and a round, using the three packed data source operands and storage into a corresponding packed data element position of an identified destination location, wherein which packed data element positions are to be added and subtracted is defined by the opcode is supported.

公开(公告)号：US20240103866A1

公开(公告)日：2024-03-28

申请号：US18217543

申请日：2023-07-01

申请人： John MORGAN ,  Deepti AGGARWAL ,  Michael ESPIG ,  H. Peter ANVIN

发明人： John MORGAN ,  Deepti AGGARWAL ,  Michael ESPIG ,  H. Peter ANVIN

IPC分类号： G06F9/30 ,  G06F7/02

CPC分类号： G06F9/30145 ,  G06F7/02 ,  G06F9/30105

摘要： Detailed herein are examples of instructions and their hardware support for floating-point comparison that makes use of the distinction between signed integer comparison and unsigned integer comparison to make an analogous distinction between floating-point relationships including unordered and those that do not. These instructions may reduce the number of instructions required to compare and conditionally execute operations in a program, including instructions to load values and instructions to explicitly test for the unordered condition.

公开(公告)号：US20240103872A1

公开(公告)日：2024-03-28

申请号：US18192500

申请日：2023-03-29

申请人： John MORGAN ,  Deepti AGGARWAL ,  Michael ESPIG

发明人： John MORGAN ,  Deepti AGGARWAL ,  Michael ESPIG

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30014 ,  G06F9/30036

摘要： Techniques for performing floating-point to integer conversion with saturation are described. In some examples, an instruction is executed to perform the conversion. In some examples, a single instruction to include at least one or more fields for an opcode and one or more fields for location information for at least a first source operand and a destination operand, wherein the opcode is to indicate execution circuitry is to convert, using truncation or saturation, each floating-point data element of at least the first source operand to an integer value and store the integer value into a corresponding data element position of the destination operand, wherein truncation is to be used when a conversion is inexact and saturation is to be used when a conversion overflows.