公开(公告)号：US20200097298A1

公开(公告)日：2020-03-26

申请号：US16140294

申请日：2018-09-24

申请人： CHRISTOPHER J. HUGHES ,  BRET TOLL ,  ALEXANDER HEINECKE ,  DAN BAUM ,  ELMOUSTAPHA OULD-AHMED-VALL ,  RAANAN SADE ,  ROBERT VALENTINE ,  MARK CHARNEY

发明人： CHRISTOPHER J. HUGHES ,  BRET TOLL ,  ALEXANDER HEINECKE ,  DAN BAUM ,  ELMOUSTAPHA OULD-AHMED-VALL ,  RAANAN SADE ,  ROBERT VALENTINE ,  MARK CHARNEY

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F15/80

摘要： An apparatus and method for processing array of structures (AoS) and structure of arrays (SoA) data. For example, one embodiment of a processor comprises: a destination tile register to store data elements in a structure of arrays (SoA) format; a first source tile register to store indices associated with the data elements; instruction fetch circuitry to fetch an array of structures (AoS) gather instruction comprising operands identifying the first source tile register and the destination tile register; a decoder to decode the AoS gather instruction; and execution circuitry to determine a plurality of system memory addresses based on the indices from the first source tile register, to read data elements from the system memory addresses in an AoS format, and to load the data elements to the destination tile register in an SoA format.

公开(公告)号：US20190042245A1

公开(公告)日：2019-02-07

申请号：US16146854

申请日：2018-09-28

申请人： Bret TOLL ,  Alexander F. HEINECKE ,  Christopher J. HUGHES ,  Ronen ZOHAR ,  Michael ESPIG ,  Dan BAUM ,  Raanan SADE ,  Robert VALENTINE

发明人： Bret TOLL ,  Alexander F. HEINECKE ,  Christopher J. HUGHES ,  Ronen ZOHAR ,  Michael ESPIG ,  Dan BAUM ,  Raanan SADE ,  Robert VALENTINE

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06

摘要： Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

公开(公告)号：US09026829B2

公开(公告)日：2015-05-05

申请号：US12890652

申请日：2010-09-25

申请人： Eliezer Weissmann ,  Alon Naveh ,  Nadav Shulman ,  Hisham Abu Salah ,  Dan Baum

发明人： Eliezer Weissmann ,  Alon Naveh ,  Nadav Shulman ,  Hisham Abu Salah ,  Dan Baum

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F12/08

CPC分类号： G06F1/3203 ,  G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

摘要： Methods and apparatus to optimize package level power state usage are described. In one embodiment, a processor control logic receives a request to enter a lower power consumption state (such as a package level deeper sleep state). The control logic determines the time difference or delta between a last entry into the lower power consumption state and the current time. The control logic then causes the flushing of a last level cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state. Other embodiments are also claimed and disclosed.

摘要翻译： 描述了优化封装级功率状态使用的方法和设备。 在一个实施例中，处理器控制逻辑接收到进入较低功耗状态（诸如封装级更深的睡眠状态）的请求。 控制逻辑确定进入较低功耗状态的最后一个入口与当前时间之间的时差或增量。 然后，控制逻辑基于时间差与对应于较低功耗状态的阈值的比较，引起最后一级高速缓冲存储器的刷新。 还要求和公开其它实施例。

公开(公告)号：US08539269B2

公开(公告)日：2013-09-17

申请号：US13077618

申请日：2011-03-31

申请人： Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Doron Rajwan ,  Kosta Luria ,  Ronny Korner ,  Dan Baum

发明人： Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Doron Rajwan ,  Kosta Luria ,  Ronny Korner ,  Dan Baum

IPC分类号： G06F1/32

CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3243 ,  G06F11/004 ,  G06F11/3024 ,  G06F11/3058 ,  G06F11/348 ,  G06F2201/81 ,  G06F2201/86 ,  Y02D10/152

摘要： An apparatus may comprise one or more processor cores of a processor and a set of current limiters. Each current limiter may be coupled to a respective processor core and arranged to monitor processor activity in the processor, to compare the processor activity to one or more current limits of multiple current limits; and to initiate a current-limiting action when the one or more current limits is exceeded.

摘要翻译： 设备可以包括处理器的一个或多个处理器核心和一组限流器。 每个限流器可以耦合到相应的处理器核心并且被布置成监视处理器中的处理器活动，以将处理器活动与多个电流限制的一个或多个电流限制进行比较; 并且当超过一个或多个电流限制时启动限流动作。

公开(公告)号：US20090327656A1

公开(公告)日：2009-12-31

申请号：US12122221

申请日：2008-05-16

申请人： Dan Baum ,  Dany Rybnikov ,  Erfraim Rotem ,  Ronny Komer

发明人： Dan Baum ,  Dany Rybnikov ,  Erfraim Rotem ,  Ronny Komer

IPC分类号： G06F9/318

CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3419 ,  G06F11/3476 ,  G06F2201/86 ,  G06F2201/88 ,  Y02D10/126 ,  Y02D10/172

摘要： Techniques are disclosed involving techniques that may dynamically adjust processor (e.g., CPU) performance. For instance, an apparatus includes a counter, an efficiency determination module, and a management module. The counter determines a number of event occurrences, wherein each of the event occurrences involves a processor component (e.g., a processor core) awaiting a response from a device. The efficiency determination module determines an efficiency metric based on the number of event occurrences. The management module establishes one or more operational characteristics for the processor component that correspond to the efficiency metric. Other embodiments are described and claimed.

摘要翻译： 公开了涉及可动态调整处理器（例如CPU）性能的技术的技术。 例如，一种装置包括计数器，效率确定模块和管理模块。 计数器确定事件发生的次数，其中每个事件发生涉及等待来自设备的响应的处理器组件（例如，处理器核心）。 效率确定模块基于事件发生的次数来确定效率度量。 管理模块为处理器组件建立一个或多个对应于效率度量的操作特性。 描述和要求保护其他实施例。

公开(公告)号：US20120079304A1

公开(公告)日：2012-03-29

申请号：US12890652

申请日：2010-09-25

申请人： Eliezer Weissmann ,  Alon Naveh ,  Nadav Shulman ,  Hisham Abu Salah ,  Dan Baum

发明人： Eliezer Weissmann ,  Alon Naveh ,  Nadav Shulman ,  Hisham Abu Salah ,  Dan Baum

IPC分类号： G06F1/32 ,  G06F12/08

CPC分类号： G06F1/3203 ,  G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

摘要： Methods and apparatus to optimize package level power state usage are described. In one embodiment, a processor control logic receives a request to enter a lower power consumption state (such as a package level deeper sleep state). The control logic determines the time difference or delta between a last entry into the lower power consumption state and the current time. The control logic then causes the flushing of a last level cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state. Other embodiments are also claimed and disclosed.

摘要翻译： 描述了优化封装级功率状态使用的方法和设备。 在一个实施例中，处理器控制逻辑接收到进入较低功耗状态（诸如封装级更深的睡眠状态）的请求。 控制逻辑确定进入较低功耗状态的最后一个入口与当前时间之间的时差或增量。 然后，控制逻辑基于时间差与对应于较低功耗状态的阈值的比较，引起最后一级高速缓冲存储器的刷新。 还要求和公开其它实施例。

公开(公告)号：US20100083009A1

公开(公告)日：2010-04-01

申请号：US12242000

申请日：2008-09-30

申请人： Efraim Rotem ,  Dan Baum ,  Doron Rajwan ,  Omer Vikinski ,  Ronny Korner ,  Kosta Luria

发明人： Efraim Rotem ,  Dan Baum ,  Doron Rajwan ,  Omer Vikinski ,  Ronny Korner ,  Kosta Luria

IPC分类号： G06F1/00

CPC分类号： G06F1/3203

摘要： Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed.

摘要翻译： 本文描述了用于管理处理单元的功率的方法，装置和系统。 一些实施例包括确定由处理单元消耗的电流的当前分量的子集的电压变化。 其他实施例包括检测处理单元的处理核心上的架构事件并且建立各种动作以减少对核心的指令的输入速率。 可以描述和要求保护其他实施例。

公开(公告)号：US20240329994A1

公开(公告)日：2024-10-03

申请号：US18193237

申请日：2023-03-30

申请人： Uri Sherman ,  Dan Baum ,  Menachem Adelman ,  Amit Gradstein

发明人： Uri Sherman ,  Dan Baum ,  Menachem Adelman ,  Amit Gradstein

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036

摘要： Techniques for converting floating-point to integer are described. An example of an instruction to perform such a conversion includes fields for an opcode, an identification of location of a packed data source operand, an identification of location of a packed data destination operand, an indication of a location in each packed data element of the packed data destination to store an 8-bit integer (INT8) value, wherein the opcode is to indicate to conversion circuitry is to downconvert data of each packed data element of the packed data source operand to an INT8 value and make available for storage the INT8 value in the identified location of a corresponding packed data element of the packed data destination.

公开(公告)号：US20200310800A1

公开(公告)日：2020-10-01

申请号：US16366941

申请日：2019-03-27

申请人： Jorge PARRA ,  Dan BAUM ,  Robert CHAPPELL ,  Michael ESPIG ,  Varghese GEORGE ,  Alexander HEINECKE ,  Christopher HUGHES ,  Subramaniam MAIYURAN ,  Elmoustapha OULD-AHMED-VALL ,  Prasoonkumar SURTI ,  Ronen ZOHAR

发明人： Jorge PARRA ,  Dan BAUM ,  Robert CHAPPELL ,  Michael ESPIG ,  Varghese GEORGE ,  Alexander HEINECKE ,  Christopher HUGHES ,  Subramaniam MAIYURAN ,  Elmoustapha OULD-AHMED-VALL ,  Prasoonkumar SURTI ,  Ronen ZOHAR

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/34 ,  G06F17/11

摘要： Methods and apparatus for approximation using polynomial functions are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry is to decode an instruction, where the instruction comprises a first operand specifying an output location and a second operand specifying a plurality of data element values to be computed. The execution circuitry is to execute the decoded instruction. The execution includes to compute a result for each of the plurality of data element values using a polynomial function to approximate a complex function, where the computation uses coefficients stored in a lookup location for the complex function, and where data element values within different data element value ranges use different sets of coefficients. The execution further includes to store results of the computation in the output location.

公开(公告)号：US08386807B2

公开(公告)日：2013-02-26

申请号：US12242000

申请日：2008-09-30

申请人： Efraim Rotem ,  Dan Baum ,  Rajwan Doron ,  Omer Vikinski ,  Ronny Korner ,  Kosta Luria

发明人： Efraim Rotem ,  Dan Baum ,  Rajwan Doron ,  Omer Vikinski ,  Ronny Korner ,  Kosta Luria

IPC分类号： G06F1/00

CPC分类号： G06F1/3203

摘要： Methods, apparatuses, and systems for managing power of a processing unit are described herein. Some embodiments include determining a voltage variation of a subset of current components of a current consumed by a processing unit. Other embodiments include detecting architectural events on a processing core of the processing unit and instituting various actions to reduce an input rate of instructions to the core. Other embodiments may be described and claimed.

摘要翻译： 本文描述了用于管理处理单元的功率的方法，装置和系统。 一些实施例包括确定由处理单元消耗的电流的当前分量的子集的电压变化。 其他实施例包括检测处理单元的处理核心上的架构事件并且建立各种动作以减少对核心的指令的输入速率。 可以描述和要求保护其他实施例。