公开(公告)号：US5991196A

公开(公告)日：1999-11-23

申请号：US991423

申请日：1997-12-16

申请人： Joseph A. Thomsen ,  Timothy J. Phoenix ,  Brian Boles ,  Henry Pena ,  Gordon E. Luke

发明人： Joseph A. Thomsen ,  Timothy J. Phoenix ,  Brian Boles ,  Henry Pena ,  Gordon E. Luke

IPC分类号： G11C16/02 ,  G11C8/12 ,  G11C16/16 ,  G11C16/04

CPC分类号： G11C8/12 ,  G11C16/16

摘要： An improved reprogrammable memory device permits definition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page. The improved reprogrammable memory device with variable page size comprises an array of memory cells where the memory cells are arranged in rows and columns; address decode logic coupled to the array of memory cells for accessing the array of memory cells; amplifier logic coupled to the array of memory cells for amplifying the voltage levels between a plurality of the memory cells and data bus when accessing the array of memory cells; column select logic coupled to the array of memory cells for determining which word from a selected row of the array of the memory cells is accessed and for connecting the plurality of memory cells to the amplifier logic; control signals coupled to the amplifier logic for accessing the array of memory cells; and, block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.

摘要翻译： 改进的可再编程存储器件允许定义尺寸可变的存储器单元阵列内的页面，仅擦除所定义的可变页面中包含的数据，同时不影响存储器单元阵列中的剩余数据并重新编程定义的变量页 。 具有可变页大小的改进的可重编程存储器件包括其中存储器单元以行和列布置的存储器单元阵列; 地址解码逻辑，其耦合到用于访问存储器单元阵列的存储器单元阵列; 放大器逻辑耦合到存储器单元阵列，用于在访问存储器单元阵列时放大多个存储器单元和数据总线之间的电压电平; 列选择逻辑，其耦合到存储器单元阵列，用于确定来自存储器单元的阵列的选定行的哪个字被访问，并将多个存储器单元连接到放大器逻辑; 耦合到放大器逻辑的用于访问存储器单元阵列的控制信号; 以及耦合到地址解码逻辑的块使能信号，用于在待擦除的存储器单元阵列内改变页大小。