公开(公告)号：US06472291B1

公开(公告)日：2002-10-29

申请号：US09492541

申请日：2000-01-27

申请人： Joseph E. Page ,  Jonathan P. Davis ,  Scott W. Bailey

发明人： Joseph E. Page ,  Jonathan P. Davis ,  Scott W. Bailey

IPC分类号： H01L2176

CPC分类号： G11C5/063 ,  H03K19/018521 ,  H03K19/018592 ,  H03K19/09429

摘要： A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention includes providing a semiconductor wafer having trenches formed in a trench region of a substrate, and forming a dielectric layer on the semiconductor wafer to fill the trenches whereby up features form on flat surfaces of the wafer. An edge portion of the semiconductor wafer is polished to remove a portion of the dielectric layer about the edge portions of the semiconductor wafer. The dielectric layer is polished across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the trench regions and the up features in a single polish step such that a mask step and etch step for reducing the up features are eliminated from the polishing process.

摘要翻译： 根据本发明的用于平坦化半导体晶片上的介电层同时消除掩模和蚀刻步骤的方法包括提供半导体晶片，其具有形成在衬底的沟槽区域中的沟槽，并且在半导体晶片上形成介电层 以填充沟槽，由此在晶片的平坦表面上形成上部特征。 半导体晶片的边缘部分被抛光以除去半导体晶片的边缘部分周围的介电层的一部分。 通过使用单个非堆叠的抛光垫和浆料在单个抛光步骤中平坦化沟槽区域和上部特征，使整个半导体晶片的电介质层被抛光，使得用于减小特征的掩模步骤和蚀刻步骤是 从抛光过程中消除。