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1.发明授权Buffer placement with respect to data flow direction and placement area geometry in hierarchical VLS designs 有权相对于分层VLS设计中的数据流方向和放置区几何的缓冲放置公开(公告)号：US07827513B2
公开(公告)日：2010-11-02
申请号：US11870728
申请日：2007-10-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported. Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.
摘要翻译： 用于在VLSI分级芯片设计中识别和修改父缓冲区布置的方法，其导致布线跟踪关于数据流和父放置区几何的低效。 审查父放置区域，并将子集分类为区分为水平插槽或垂直插槽。 对数据流方向是强水平或强垂直的情况进行缓冲数据流的缓冲。 报告缓冲区缓冲区数据流向与缓冲区驻留的父放置槽方向相同的方向的情况。 另外，试图找到除了排列方向与数据流相同方向的父放置区之外的缓冲区的有效放置位置。
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2.发明申请Buffer Placement with Respect to Data Flow Direction and Placement Area Geometry in Hierarchical VLS Designs 有权缓冲放置相对于数据流方向和放置区几何分层VLS设计公开(公告)号：US20090100397A1
公开(公告)日：2009-04-16
申请号：US11870728
申请日：2007-10-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either Strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported, Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.
摘要翻译： 用于在VLSI分级芯片设计中识别和修改父缓冲区布置的方法，其导致布线跟踪关于数据流和父放置区几何的低效。 审查父放置区域，并将子集分类为区分为水平插槽或垂直插槽。 对数据流方向为强水平或强垂直的情况进行缓冲数据流的缓冲。 报告缓冲区缓冲区数据流向与缓冲区驻留的父放置槽方向相同的情况。另外，尝试找到缓冲区的有效放置位置，不包括相同方向的父放置区域 作为数据流。
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3.发明授权Method, system, and computer program product for hierarchical integrated circuit repartitioning 失效分层集成电路重新分配的方法，系统和计算机程序产品公开(公告)号：US07568176B2
公开(公告)日：2009-07-28
申请号：US11757457
申请日：2007-06-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list.
摘要翻译： 提供了一种用于分级集成电路重新分配的方法，系统和计算机程序产品。 该方法包括接收一个或多个互连元件的父级放置数据，并且指定至少一个子级以从母级接收一个或多个互连元件的下推。 对于被指定为接收一个或多个互连元件的下推的每个孩子，该方法还包括确定儿童的物理覆盖区域，识别儿童的物理覆盖区域内的一个或多个互连元件中的哪一个向下推入 孩子，为孩子生成互连元件下拉列表，包括布线层信息，以及输出互连元件下推列表。
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4.发明申请METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HIERARCHICAL INTEGRATED CIRCUIT REPARTITIONING 失效用于分层整合电路分配的方法，系统和计算机程序产品公开(公告)号：US20080301607A1
公开(公告)日：2008-12-04
申请号：US11757457
申请日：2007-06-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list.
摘要翻译： 提供了一种用于分级集成电路重新分配的方法，系统和计算机程序产品。 该方法包括接收一个或多个互连元件的父级放置数据，并且指定至少一个子级以从母级接收一个或多个互连元件的下推。 对于被指定为接收一个或多个互连元件的下推的每个孩子，该方法还包括确定儿童的物理覆盖区域，识别儿童的物理覆盖区域内的一个或多个互连元件中的哪一个向下推入 孩子，为孩子生成互连元件下拉列表，包括布线层信息，以及输出互连元件下推列表。
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5.发明授权Method for identification and removal of non-timing critical wire routes from congestion region 失效从拥塞地区识别和去除非定时关键线路的方法公开(公告)号：US06904585B2
公开(公告)日：2005-06-07
申请号：US10408206
申请日：2003-04-04
CPC分类号： G06F17/5077
摘要： A method for identifying and modifying, in a VLSI chip design, wire routes within a region of wiring congestion that can be routed around that region without inducing timing violations by the insertion and proper placement of inverters. Circuits and nets are examined in the vicinity of the wiring congestion to determine those nets with high potential to drive a route outside the region. Circuit locations are analyzed to determine if the net connecting them creates a path through the region of wiring congestion. Timing slacks are derived from the timing reports for such nets and compared against a timing value representing the additional delay of using an inverter pair to drive the wire route outside the region of wiring congestion. If a net has sufficient timing slack, it is buffered with an inverter pair which is then placed in a manner as to force the wire routes for the modified path around the region of wiring congestion, thereby reducing the wire utilization within the region.
摘要翻译： 用于在VLSI芯片设计中识别和修改在布线拥塞区域内的线路路由的方法，其可以围绕该区域布线，而不会通过插入和正确布置逆变器而引起定时违规。 在布线拥挤附近检查电路和网络，以确定具有高电位驱动该地区以外的路线的网络。 分析电路位置以确定连接它们的网络是否通过布线拥塞区域创建路径。 定时松弛源自这种网络的定时报告，并与表示使用逆变器对以驱动布线拥塞区域之外的线路路由的附加延迟的定时值进行比较。 如果网络具有足够的定时松弛，则用逆变器对进行缓冲，然后将其布置成强制线路沿着布线拥塞区域的修改路径，从而减少该区域内的线路利用。
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公开(公告)号：US08010922B2
公开(公告)日：2011-08-30
申请号：US12032762
申请日：2008-02-18
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.
摘要翻译： 缓冲器放置在耦合到IC器件中的实体的输入和输出引脚的选定网络上。 这包括在分别缓冲实体的网络和连续迭代中的缓冲之前加载实体的选定输入和输出引脚，其中包括在选定的输入引脚上设置人工负载。 当前迭代中的缓冲被限制为i）在当前迭代实体上的接收器的当前迭代实体上缓冲网络，以及ii）直接耦合到已经被缓冲的紧邻相邻实体的相应网络的当前迭代实体上的缓冲网 在前面的一个迭代中，但是仅当已经缓冲的网络耦合到其自身网络上的接收器或已经经由一个或多个前述迭代缓冲的网络的一些其它已经缓冲的网络上的接收器时。
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公开(公告)号：US06990648B2
公开(公告)日：2006-01-24
申请号：US10408203
申请日：2003-04-04
申请人： Joseph J. Palumbo
发明人： Joseph J. Palumbo
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for identifying, in a VLSI chip design, circuits placed in an region of wiring congestion which can be replaced such that wiring tracks are freed up due to decreased net lengths without any pin to pin segment increasing in length. Circuits placed within the region of wiring congestion are identified and examined to determine the circuits they connect to. The placements of the connected circuits are analyzed to derive a rectangle of connectivity. Each of the originally identified circuits are then checked to determine if they are placed within their associated rectangle of connectivity. If not, the distance between the circuit and rectangle is calculated along with a recommended placement location, both of which are reported along with the circuit. The recommended placement location is a point along the border of the rectangle such that replacement of the circuit at the location reduces all circuit net lengths without increasing any pin to pin segment. In this way, wiring tracks are freed up without any potential for increased path delays.
摘要翻译： 用于在VLSI芯片设计中识别放置在可以被替换的布线拥塞区域中的电路的方法，使得布线轨道由于净长度的减小而没有任何引脚到引脚段的长度增加而被释放。 识别和检查放置在布线拥塞区域内的电路，以确定它们连接的电路。 分析连接电路的布局以得到连接矩形。 然后检查每个原始识别的电路以确定它们是否被放置在其相关的连接矩形内。 如果不是，则计算电路和矩形之间的距离以及推荐的放置位置，两者都与电路一起报告。 推荐的放置位置是沿着矩形边界的点，以便在该位置处更换电路可以减少所有电路网长度，而不会增加任何引脚到引脚段。 以这种方式，布线轨道被释放，没有增加路径延迟的潜力。
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公开(公告)号：US20090210842A1
公开(公告)日：2009-08-20
申请号：US12032762
申请日：2008-02-18
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Buffers are placed on selected nets coupled to input and output pins of entities in an IC device. This includes loading selected input and output pins of entities prior to respectively buffering nets of the entities and buffering in successive iterations, which includes setting artificial loads on selected input pins. The buffering in a current iteration is limited to i) buffering nets on the current iteration entity for receivers on the current iteration entity and ii) buffering nets on the current iteration entity directly coupled to respective nets of an immediately adjacent entity that has been buffered already in a preceding one of iterations, but only if the already buffered net is coupled to a receiver on its own net or a receiver on some other already buffered net via nets that have all been buffered via one or more of the preceding iterations.
摘要翻译： 缓冲器放置在耦合到IC器件中的实体的输入和输出引脚的选定网络上。 这包括在分别缓冲实体的网络和连续迭代中的缓冲之前加载实体的选定输入和输出引脚，其中包括在选定的输入引脚上设置人工负载。 当前迭代中的缓冲被限制为i）在当前迭代实体上的接收器的当前迭代实体上缓冲网络，以及ii）直接耦合到已经被缓冲的紧邻相邻实体的相应网络的当前迭代实体上的缓冲网 在前面的一个迭代中，但是仅当已经缓冲的网络耦合到其自身网络上的接收器或已经经由一个或多个前述迭代缓冲的网络的一些其它已经缓冲的网络上的接收器时。
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