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    Buffer placement with respect to data flow direction and placement area geometry in hierarchical VLS designs
    1.
    发明授权
    Buffer placement with respect to data flow direction and placement area geometry in hierarchical VLS designs 有权
    相对于分层VLS设计中的数据流方向和放置区几何的缓冲放置

    公开(公告)号：US07827513B2

    公开(公告)日：2010-11-02

    申请号：US11870728

    申请日：2007-10-11

    申请人： Joseph J. Palumbo ,  Christopher J. Berry ,  Adam R. Jalkowski

    发明人： Joseph J. Palumbo ,  Christopher J. Berry ,  Adam R. Jalkowski

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported. Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.

    摘要翻译： 用于在VLSI分级芯片设计中识别和修改父缓冲区布置的方法，其导致布线跟踪关于数据流和父放置区几何的低效。 审查父放置区域，并将子集分类为区分为水平插槽或垂直插槽。 对数据流方向是强水平或强垂直的情况进行缓冲数据流的缓冲。 报告缓冲区缓冲区数据流向与缓冲区驻留的父放置槽方向相同的方向的情况。 另外，试图找到除了排列方向与数据流相同方向的父放置区之外的缓冲区的有效放置位置。

    Buffer Placement with Respect to Data Flow Direction and Placement Area Geometry in Hierarchical VLS Designs
    2.
    发明申请
    Buffer Placement with Respect to Data Flow Direction and Placement Area Geometry in Hierarchical VLS Designs 有权
    缓冲放置相对于数据流方向和放置区几何分层VLS设计

    公开(公告)号：US20090100397A1

    公开(公告)日：2009-04-16

    申请号：US11870728

    申请日：2007-10-11

    申请人： Joseph J. Palumbo ,  Christopher J. Berry ,  Adam R. Jalkowski

    发明人： Joseph J. Palumbo ,  Christopher J. Berry ,  Adam R. Jalkowski

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either Strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported, Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.

    摘要翻译： 用于在VLSI分级芯片设计中识别和修改父缓冲区布置的方法，其导致布线跟踪关于数据流和父放置区几何的低效。 审查父放置区域，并将子集分类为区分为水平插槽或垂直插槽。 对数据流方向为强水平或强垂直的情况进行缓冲数据流的缓冲。 报告缓冲区缓冲区数据流向与缓冲区驻留的父放置槽方向相同的情况。另外，尝试找到缓冲区的有效放置位置，不包括相同方向的父放置区域 作为数据流。

    Computer program product, apparatus, and method for inserting components in a hierarchical chip design
    5.
    发明授权
    Computer program product, apparatus, and method for inserting components in a hierarchical chip design 有权
    用于在分层芯片设计中插入组件的计算机程序产品，装置和方法

    公开(公告)号：US08261224B2

    公开(公告)日：2012-09-04

    申请号：US12034644

    申请日：2008-02-20

    申请人： Frank Malgioglio ,  Christopher J. Berry

    发明人： Frank Malgioglio ,  Christopher J. Berry

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505

    摘要： Components are inserted into a cell-based current chin design with multiple levels of nested hierarchy. A selection of components having various silicon densities to insert into the current chip design is received. The components are inserted into the current chip design such that the components do not touch or overlap existing circuits or silicon shapes in the current chip design. The components are inserted such that components having highest silicon densities are placed further away from the existing circuits or silicon shapes than components having lower silicon densities.

    摘要翻译： 将组件插入到具有多级嵌套层次结构的基于单元格的当前下巴设计中。 接收具有插入到当前芯片设计中的具有各种硅密度的组件的选择。 将部件插入到当前芯片设计中，使得组件在当前芯片设计中不接触或重叠现有电路或硅形状。 这些部件被插入，使得具有最高硅密度的部件被放置成远离现有的电路或硅形状，而不是具有较低硅密度的部件。

    Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy
    6.
    发明授权
    Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy 有权
    优化具有多层次结构的集成电路中的扫描链的方法

    公开(公告)号：US07987400B2

    公开(公告)日：2011-07-26

    申请号：US12035500

    申请日：2008-02-22

    申请人： Christopher J. Berry ,  Lawrence David Curley ,  Patrick James Meaney ,  Diana Lynn Orf

    发明人： Christopher J. Berry ,  Lawrence David Curley ,  Patrick James Meaney ,  Diana Lynn Orf

    IPC分类号： G01R31/28 ,  G06F17/50

    CPC分类号： G01R31/318536

    摘要： A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.

    摘要翻译： 一种用于优化集成电路中具有多层次层次结构的扫描链的方法，可以解决无限链和树桩，并分开所有其他链和树桩。 通过将链包围的区域和残端的起始点和终点分成由多个网格框组成的网格，并且将网格框确定为网格框连接路由以访问所有网格框，来优化无限链和树桩 的起始点和终点之间的网格框通过运行路由算法的计算机。 优化的所有其他链和树桩被随机地分配给一个树桩，一个可以通过该树桩物理达到的链，并根据附加链中的锁存数，其物理位置和锁存数量向该残基添加一个附加链 已分配

    Double data rate chaining for synchronous DDR interfaces
    9.
    发明授权
    Double data rate chaining for synchronous DDR interfaces 失效
    双数据速率链接同步DDR接口

    公开(公告)号：US07739538B2

    公开(公告)日：2010-06-15

    申请号：US11426651

    申请日：2006-06-27

    申请人： Michael Fee ,  Patrick J. Meaney ,  Christopher J. Berry ,  Jonathan Y. Chen ,  Alan P. Wagstaff

    发明人： Michael Fee ,  Patrick J. Meaney ,  Christopher J. Berry ,  Jonathan Y. Chen ,  Alan P. Wagstaff

    IPC分类号： G06F5/06 ,  G11C8/16

    CPC分类号： G06F13/4217

    摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.

    摘要翻译： 一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收​​的数据的每一半。 每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。 首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。 数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。 在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。 这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。

    Process for managing complex pre-wired net segments in a VLSI design
    10.
    发明授权
    Process for managing complex pre-wired net segments in a VLSI design 有权
    在VLSI设计中管理复杂的预先有线网段的过程

    公开(公告)号：US07681169B2

    公开(公告)日：2010-03-16

    申请号：US11846577

    申请日：2007-08-29

    申请人： Christopher J. Berry ,  Michael A. Bowen ,  Michael R. Scheuermann ,  Michael H. Wood

    发明人： Christopher J. Berry ,  Michael A. Bowen ,  Michael R. Scheuermann ,  Michael H. Wood

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.

    摘要翻译： 使用烟道预先接线多层金属的方法包括以下步骤：接收包括烟道几何形状和烟道特性的信息; 生成针对流感的设计的多个路由模式; 识别要在设计中预先布线的宏实例终端; 在设计中选择用于宏实例终端的路由模式中的至少一个以避免阻塞; 并实例化设计，使得烟道可以被操纵为过孔。