公开(公告)号：US20050033906A1

公开(公告)日：2005-02-10

申请号：US10932395

申请日：2004-09-01

申请人： Josh Mastronarde ,  Aditya Sreenivas ,  Thomas Piazza

发明人： Josh Mastronarde ,  Aditya Sreenivas ,  Thomas Piazza

IPC分类号： G06F13/16 ,  G06F13/18 ,  G06F12/00

CPC分类号： G06F13/161 ,  G06F13/18

摘要： Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

摘要翻译： 本发明的实施例提供了一种用于将芯片组和图形业务引导到系统存储器的存储器仲裁器。 页面一致性和优先级用于优化内存带宽利用率，并保证等时显示请求的延迟。 仲裁器还包含一种防止CPU请求饥饿较低优先级请求的机制。 因此，存储器仲裁器提供了一种简单易于验证的架构，防止CPU不利地挨饿低优先级代理，并利用宽限期和存储器页面检测来优化仲裁交换机，从而增加内存带宽利用率。