公开(公告)号：US20100271069A1

公开(公告)日：2010-10-28

申请号：US12714878

申请日：2010-03-01

申请人： Joung Yeal Kim ,  Young Hyun Jun ,  Bai Sun Kong

发明人： Joung Yeal Kim ,  Young Hyun Jun ,  Bai Sun Kong

IPC分类号： H03K19/0175 ,  G11C7/00

CPC分类号： H04L25/0278 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  H03K19/017509

摘要： An input/output circuit includes an I/O node connected to a pull up and pull down circuit having a pull up and pull down transistors. Data is sent and received at through the I/O node. A level shifter provides voltages including a supply voltage and a high voltage higher than the supply voltage. A signal control circuit controls the voltage level applied to the pull up and pull down circuit. During a data input mode, data is received at the I/O node and the pull up transistor is biased at the high voltage to cut off the pull up transistor. During a data output mode, data is output at the I/O node and the pull down transistor pulls down the I/O node to ground when the output data is low, and the pull up transistor is activated when the output data is high.

摘要翻译： 输入/输出电路包括连接到具有上拉和下拉晶体管的上拉和下拉电路的I / O节点。 通过I / O节点发送和接收数据。 电平移位器提供包括电源电压和高于电源电压的高电压的电压。 信号控制电路控制施加到上拉和下拉电路的电压电平。 在数据输入模式期间，在I / O节点处接收数据，并且上拉晶体管被偏置在高电压以截止上拉晶体管。 在数据输出模式下，在I / O节点输出数据，当输出数据为低电平时，下拉晶体管将I / O节点拉低至地，当输出数据为高电平时，上拉晶体管被激活。

公开(公告)号：US08004311B2

公开(公告)日：2011-08-23

申请号：US12714878

申请日：2010-03-01

申请人： Joung Yeal Kim ,  Young Hyun Jun ,  Bai Sun Kong

发明人： Joung Yeal Kim ,  Young Hyun Jun ,  Bai Sun Kong

IPC分类号： H03K19/0175

CPC分类号： H04L25/0278 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  H03K19/017509

摘要： An input/output circuit includes an I/O node connected to a pull up and pull down circuit having a pull up and pull down transistors. Data is sent and received at through the I/O node. A level shifter provides voltages including a supply voltage and a high voltage higher than the supply voltage. A signal control circuit controls the voltage level applied to the pull up and pull down circuit. During a data input mode, data is received at the I/O node and the pull up transistor is biased at the high voltage to cut off the pull up transistor. During a data output mode, data is output at the I/O node and the pull down transistor pulls down the I/O node to ground when the output data is low, and the pull up transistor is activated when the output data is high.

摘要翻译： 输入/输出电路包括连接到具有上拉和下拉晶体管的上拉和下拉电路的I / O节点。 通过I / O节点发送和接收数据。 电平移位器提供包括电源电压和高于电源电压的高电压的电压。 信号控制电路控制施加到上拉和下拉电路的电压电平。 在数据输入模式期间，在I / O节点处接收数据，并且上拉晶体管被偏置在高电压以截止上拉晶体管。 在数据输出模式下，在I / O节点输出数据，当输出数据为低电平时，下拉晶体管将I / O节点拉低至地，当输出数据为高电平时，上拉晶体管被激活。

公开(公告)号：US20090185437A1

公开(公告)日：2009-07-23

申请号：US12034556

申请日：2008-02-20

申请人： Bai Sun Kong ,  Sung Chan Kang ,  Byung Hwa Jung

发明人： Bai Sun Kong ,  Sung Chan Kang ,  Byung Hwa Jung

IPC分类号： G11C7/00 ,  G11C8/00 ,  H03K3/00

CPC分类号： G11C11/412 ,  H03K3/012 ,  H03K3/356121

摘要： Disclosed is a clock-based data storage device, which includes a dual pulse generating device and a data starge device having two dynamic nodes for prior chargement/dischargement. The clock-based data storage device includes a dual pulse generating unit which delays a clock signal and then outputs a first clock signal corresponding to inversion of a clock signal and a second clock signal corresponding to the clock signal by using the delayed clock signal when the clock signal shifts, a pull-up wait for outputting a pull-up output signal to an output port, based on the first clock signal outputted from the dual pulse generating unit and an input data signal which has beeb inputted, a pull-down unit for outputting a pull-down output signal to the output port, based on the second clock signal outputted from the dual pulse generating unit and the input data signal inputted which has been inputted, and a latch unit which is disposed between the pull-up and pull-down units, and the output port so as to store at least one output signal outputted f roars the pull-down unit as well as the pull-down unit.

摘要翻译： 公开了一种基于时钟的数据存储装置，其包括双脉冲发生装置和具有两个动态节点用于事先充电/放电的数据扩充装置。 基于时钟的数据存储装置包括双脉冲发生单元，其延迟时钟信号，然后通过使用延迟的时钟信号输出对应于时钟信号的反相的第一时钟信号和对应于时钟信号的第二时钟信号 基于从双脉冲发生单元输出的第一时钟信号和输入了贝贝的输入数据信号，上拉等待输出端口的上拉输出信号的上拉等待时间信号移位，下拉单元 用于基于从双脉冲发生单元输出的第二时钟信号和输入的输入数据信号向输出端口输出下拉输出信号;以及锁存单元，其设置在上拉和下拉 下拉单元和输出端口，以便存储输出的至少一个输出信号和下拉单元以及下拉单元。

公开(公告)号：US07724605B2

公开(公告)日：2010-05-25

申请号：US12034556

申请日：2008-02-20

申请人： Bai Sun Kong ,  Sung Chan Kang ,  Byung Hwa Jung

发明人： Bai Sun Kong ,  Sung Chan Kang ,  Byung Hwa Jung

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  H03K3/012 ,  H03K3/356121

摘要： Disclosed is a clock-based data storage device, which includes a dual pulse generating device and a data starge device having two dynamic nodes for prior chargement/dischargement. The clock-based data storage device includes a dual pulse generating unit which delays a clock signal and then outputs a first clock signal corresponding to inversion of a clock signal and a second clock signal corresponding to the clock signal by using the delayed clock signal when the clock signal shifts, a pull-up wait for outputting a pull-up output signal to an output port, based on the first clock signal outputted from the dual pulse generating unit and an input data signal which has beeb inputted, a pull-down unit for outputting a pull-down output signal to the output port, based on the second clock signal outputted from the dual pulse generating unit and the input data signal inputted which has been inputted, and a latch unit which is disposed between the pull-up and pull-down units, and the output port so as to store at least one output signal outputted from the pull-down unit as well as the pull-down unit.

摘要翻译： 公开了一种基于时钟的数据存储装置，其包括双脉冲发生装置和具有两个动态节点用于事先充电/放电的数据扩充装置。 基于时钟的数据存储装置包括双脉冲发生单元，其延迟时钟信号，然后通过使用延迟的时钟信号输出对应于时钟信号的反相的第一时钟信号和对应于时钟信号的第二时钟信号 基于从双脉冲发生单元输出的第一时钟信号和输入信号输入的输入数据信号，下拉单元，时钟信号移位，上拉等待输出端口输出上拉输出信号; 用于基于从双脉冲发生单元输出的第二时钟信号和输入的输入数据信号向输出端口输出下拉输出信号;以及锁存单元，其设置在上拉和下拉 下拉单元和输出端口，以便存储从下拉单元输出的至少一个输出信号以及下拉单元。