公开(公告)号：US20080298133A1

公开(公告)日：2008-12-04

申请号：US11965552

申请日：2007-12-27

申请人： Ju In KIM ,  Ju Yeab LEE

发明人： Ju In KIM ,  Ju Yeab LEE

IPC分类号： G11C16/34 ,  G11C16/10

CPC分类号： G11C16/3436

摘要： A duel program verify operation is performed using first and second verify voltages. In order to reduce the width of a threshold voltage distribution during an incremental step pulse program implementation, data of a corresponding memory cell are verified twice using the first verify voltage and the second verify voltage. During a second verify operation using the second verify voltage, a sensing current is adjusted by controlling voltages applied as a bit line select signal and an evaluation time period. Therefore, the threshold voltage of the memory cell can be measured higher or lower than its actual value and the width of a threshold voltage distribution is reduced.

摘要翻译： 使用第一和第二验证电压执行对战程序验证操作。 为了在增量步进脉冲程序实现期间减小阈值电压分布的宽度，使用第一验证电压和第二验证电压来验证相应的存储器单元的数据两次。 在使用第二验证电压的第二验证操作期间，通过控制作为位线选择信号和评估时间段施加的电压来调节感测电流。 因此，可以将存储单元的阈值电压测量为高于或低于其实际值，并且减小阈值电压分布的宽度。

公开(公告)号：US20080247240A1

公开(公告)日：2008-10-09

申请号：US11967136

申请日：2007-12-29

申请人： Ju Yeab LEE

发明人： Ju Yeab LEE

IPC分类号： G11C11/35

CPC分类号： G11C16/0483 ,  G11C16/344

摘要： In an erase verifying method of a NAND flash memory device, a power supply voltage (Vcc) is applied to a second bit line while precharging a first bit line to a first positive voltage. Select transistors are turned on, and a ground voltage is applied to word lines of memory cell transistors. A second positive voltage is applied to source lines to which sources of the select transistors and the memory cell transistors are connected. An erased state of the memory cell transistor is verified according to whether charges accumulated in the first bit line are discharged.

摘要翻译： 在NAND闪速存储器件的擦除验证方法中，在将第一位线预充电到第一正电压的同时，向第二位线施加电源电压（Vcc）。 选择晶体管导通，并将接地电压施加到存储单元晶体管的字线。 将第二正电压施加到选择晶体管和存储单元晶体管的源极连接到的源极线。 根据第一位线中累积的电荷是否放电来验证存储单元晶体管的擦除状态。