公开(公告)号：US07073140B1

公开(公告)日：2006-07-04

申请号：US10651617

申请日：2003-08-29

申请人： Jun Li ,  Athanasius Spyrou ,  Hong Zhao ,  Hsien-Yen Chiu

发明人： Jun Li ,  Athanasius Spyrou ,  Hong Zhao ,  Hsien-Yen Chiu

IPC分类号： G06F17/90

CPC分类号： G06F17/5036

摘要： Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ration of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.

摘要翻译： 公开了一种用于执行串扰和信号完整性分析的改进方法，其中在分析片上串扰的影响时考虑多个变量，例如耦合的线长度，耦合电容的比例，侵略者和受害者驱动器类型。 通过系统地改变这些多个变量的值，可以通过对特定网络部分进行模拟/建模来预先表征潜在的串扰效应，而不是进行全芯片仿真。 从变量形成的一组模式由建模形成。 在分析过程中，检查IC设计是否存在图案，从而产生设计中串扰的预期延迟影响。

公开(公告)号：US07549134B1

公开(公告)日：2009-06-16

申请号：US11479279

申请日：2006-06-30

申请人： Jun Li ,  Athanasius Spyrou ,  Hong Zhao ,  Hsien-Yen Chiu

发明人： Jun Li ,  Athanasius Spyrou ,  Hong Zhao ,  Hsien-Yen Chiu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ratio of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.

摘要翻译： 公开了一种用于执行串扰和信号完整性分析的改进方法，其中在分析片上串扰的影响时考虑多个变量，例如耦合的线长度，耦合电容的比率以及侵略者和受害者驱动器类型。 通过系统地改变这些多个变量的值，可以通过对特定网络部分进行模拟/建模来预先表征潜在的串扰效应，而不是进行全芯片仿真。 从变量形成的一组模式由建模形成。 在分析过程中，检查IC设计是否存在图案，从而产生设计中串扰的预期延迟影响。

公开(公告)号：US06721929B2

公开(公告)日：2004-04-13

申请号：US09854146

申请日：2001-05-11

申请人： Jun Li ,  Hong Zhao ,  Hsien-Yen Chiu

发明人： Jun Li ,  Hong Zhao ,  Hsien-Yen Chiu

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A variable current source model accurately determines timing delays for designs of circuits implemented in integrated circuits. A design for an integrated circuit specifies a resistive-capacitive (“RC”) network. The RC network couples a driving point and a receiving point, and a circuit specified in the design, drives the RC network at the driving point. The variable current source model determines driving currents for the circuit at the driving point based on the RC network and a characterization model of the circuit. A timing delay between the driving point and the receiving point is determined by simulating the drive of the RC network with the driving current at the driving point.

摘要翻译： 可变电流源模型精确地确定了在集成电路中实现的电路设计的定时延迟。 集成电路的设计规定了电阻电容（“RC”）网络。 RC网络耦合驱动点和接收点以及设计中指定的电路，在驱动点驱动RC网络。 可变电流源模型基于RC网络和电路的表征模型确定驱动点处电路的驱动电流。 驱动点和接收点之间的定时延迟通过模拟驱动点处的驱动电流的RC网络的驱动来确定。

公开(公告)号：US07243320B2

公开(公告)日：2007-07-10

申请号：US11301999

申请日：2005-12-12

申请人： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

发明人： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/08

摘要： An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces a large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance memos to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.

摘要翻译： 描述了结合随机分析过程（“SAP”）的集成电路设计工具。 SAP可以应用于许多级别的电路组件，包括晶体管器件，逻辑门器件和片上系统或芯片设计。 SAP使用少量采样点或角落替换大量传统的蒙特卡罗模拟，并进行操作。 SAP是使用模型拟合过程生成可以与任何数量的性能记录一起使用以产生性能变化预测以及相应的统计信息（例如，平均三西格玛概率等）的分层方法。 SAP提供了一种有效的方式来对由于全局参数（如器件尺寸，互连布线变化，经济变化和制造变化）引起的电路或系统变化进行建模。

公开(公告)号：US08005660B2

公开(公告)日：2011-08-23

申请号：US11823601

申请日：2007-06-27

申请人： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

发明人： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/10 ,  G06F2217/12 ,  G06F2217/62 ,  Y02P90/265

摘要： An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). A hierarchical SAP process breaks an overall circuit into a plurality of subcircuits and performs circuit simulation and SAP analysis steps on each subcircuit. An integration and reduction process combines the analysis results of each subcircuit, and a final SPICE/SAP process provides a model for the overall circuit based on the subcircuits.

摘要翻译： 描述了结合随机分析过程（“SAP”）的集成电路设计工具。 SAP可以应用于许多级别的电路组件，包括晶体管器件，逻辑门器件和片上系统或芯片设计。 SAP通过使用少量采样点或角落的操作替代了大量传统的蒙特卡罗模拟。 SAP是使用模型拟合过程生成可以与任何数量的性能度量一起使用以产生性能变化预测以及相应的统计信息（例如，平均三西格玛概率等）的模型的分层方法。 分层SAP流程将整个电路分解成多个子电路，并在每个子电路上执行电路仿真和SAP分析步骤。 集成和减少流程结合了每个子电路的分析结果，最终的SPICE / SAP流程为基于子电路的整个电路提供了一个模型。

公开(公告)号：US20060150129A1

公开(公告)日：2006-07-06

申请号：US11301999

申请日：2005-12-12

申请人： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

发明人： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/08

摘要： An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.

摘要翻译： 描述了结合随机分析过程（“SAP”）的集成电路设计工具。 SAP可以应用于许多级别的电路组件，包括晶体管器件，逻辑门器件和片上系统或芯片设计。 SAP通过使用少量采样点或角落的操作替代了大量传统的蒙特卡罗模拟。 SAP是使用模型拟合过程生成可以与任何数量的性能度量一起使用以产生性能变化预测以及相应的统计信息（例如，平均三西格玛概率等）的模型的分层方法。 SAP提供了一种有效的方式来对由于全局参数（如器件尺寸，互连布线变化，经济变化和制造变化）引起的电路或系统变化进行建模。

公开(公告)号：US20080059143A1

公开(公告)日：2008-03-06

申请号：US11823601

申请日：2007-06-27

申请人： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

发明人： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/10 ,  G06F2217/12 ,  G06F2217/62 ,  Y02P90/265

摘要： An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). A hierarchical SAP process breaks an overall circuit into a plurality of subcircuits and performs circuit simulation and SAP analysis steps on each subcircuit. An integration and reduction process combines the analysis results of each subcircuit, and a final SPICE/SAP process provides a model for the overall circuit based on the subcircuits.

摘要翻译： 描述了结合随机分析过程（“SAP”）的集成电路设计工具。 SAP可以应用于许多级别的电路组件，包括晶体管器件，逻辑门器件和片上系统或芯片设计。 SAP通过使用少量采样点或角落的操作替代了大量传统的蒙特卡罗模拟。 SAP是使用模型拟合过程生成可以与任何数量的性能度量一起使用以产生性能变化预测以及相应的统计信息（例如，平均三西格玛概率等）的模型的分层方法。 分层SAP流程将整个电路分解成多个子电路，并在每个子电路上执行电路仿真和SAP分析步骤。 集成和减少流程结合了每个子电路的分析结果，最终的SPICE / SAP流程为基于子电路的整个电路提供了一个模型。