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    Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture
    1.
    发明授权
    Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture 失效
    集成电路设计制造的分层随机分析过程优化

    公开(公告)号：US08005660B2

    公开(公告)日：2011-08-23

    申请号：US11823601

    申请日：2007-06-27

    Applicant: Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

    Inventor： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

    IPC: G06F17/50

    CPC classification number: G06F17/5009 ,  G06F2217/10 ,  G06F2217/12 ,  G06F2217/62 ,  Y02P90/265

    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). A hierarchical SAP process breaks an overall circuit into a plurality of subcircuits and performs circuit simulation and SAP analysis steps on each subcircuit. An integration and reduction process combines the analysis results of each subcircuit, and a final SPICE/SAP process provides a model for the overall circuit based on the subcircuits.

    Abstract translation: 描述了结合随机分析过程（“SAP”）的集成电路设计工具。 SAP可以应用于许多级别的电路组件，包括晶体管器件，逻辑门器件和片上系统或芯片设计。 SAP通过使用少量采样点或角落的操作替代了大量传统的蒙特卡罗模拟。 SAP是使用模型拟合过程生成可以与任何数量的性能度量一起使用以产生性能变化预测以及相应的统计信息（例如，平均三西格玛概率等）的模型的分层方法。 分层SAP流程将整个电路分解成多个子电路，并在每个子电路上执行电路仿真和SAP分析步骤。 集成和减少流程结合了每个子电路的分析结果，最终的SPICE / SAP流程为基于子电路的整个电路提供了一个模型。

    Stochastic analysis process optimization for integrated circuit design and manufacture
    2.
    发明授权
    Stochastic analysis process optimization for integrated circuit design and manufacture 失效
    集成电路设计制造的随机分析过程优化

    公开(公告)号：US07243320B2

    公开(公告)日：2007-07-10

    申请号：US11301999

    申请日：2005-12-12

    Applicant: Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

    Inventor： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

    IPC: G06F17/50

    CPC classification number: G06F17/5022 ,  G06F2217/08

    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces a large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance memos to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.

    Abstract translation: 描述了结合随机分析过程（“SAP”）的集成电路设计工具。 SAP可以应用于许多级别的电路组件，包括晶体管器件，逻辑门器件和片上系统或芯片设计。 SAP使用少量采样点或角落替换大量传统的蒙特卡罗模拟，并进行操作。 SAP是使用模型拟合过程生成可以与任何数量的性能记录一起使用以产生性能变化预测以及相应的统计信息（例如，平均三西格玛概率等）的分层方法。 SAP提供了一种有效的方式来对由于全局参数（如器件尺寸，互连布线变化，经济变化和制造变化）引起的电路或系统变化进行建模。

    LED light source lampshade with self-locking and pre-tightening device
    3.
    发明授权
    LED light source lampshade with self-locking and pre-tightening device 有权

    公开(公告)号：US10578254B2

    公开(公告)日：2020-03-03

    申请号：US16262652

    申请日：2019-01-30

    Applicant: Meiling Wang

    Inventor： Meiling Wang

    IPC: F21K9/237 ,  F21V17/18 ,  F21Y115/10

    Abstract: The present invention disclosed an LED light source lampshade with a self-locking and pre-tightening device, which relates to the field of illuminating devices. The LED light source lampshade with a self-locking and pre-tightening device comprises a lampshade and a lamp body, wherein a side wall of the lampshade comprises an outer side wall of the lampshade and a plurality of connecting ribs, wherein a gap is provided between every two adjacent connecting ribs, wherein a limiting slot is provided between each connecting rib and the outer side wall of the lampshade, wherein a length of the connecting rib is greater than the length of the outer side wall of the lampshade, wherein a rotating boss is provided on an outer side surface of each of the plurality of connecting rib, so that the cross section of the side wall of the lampshade is in an approximately “concave” shape; the edge of the upper end surface of the lamp body is surrounded by a plurality of limiting slots, wherein a pre-tightening groove is provided between the adjacent two limiting ribs, wherein a self-locking groove is provided on one end of the pre-tightening groove near the guiding groove, wherein the lamp body is connected with the lampshade, wherein the rotating boss is matched with the pre-tightening groove. The LED light source lampshade with a self-locking and pre-tightening device provided by the present invention has advantages of simple structure, convenient installation and high production efficiency of the lampshade.

    LED LIGHT SOURCE LAMPSHADE WITH SELF-LOCKING AND PRE-TIGHTENING DEVICE
    4.
    发明申请
    LED LIGHT SOURCE LAMPSHADE WITH SELF-LOCKING AND PRE-TIGHTENING DEVICE 审中-公开

    公开(公告)号：US20190293244A1

    公开(公告)日：2019-09-26

    申请号：US16262652

    申请日：2019-01-30

    Applicant: Meiling Wang

    Inventor： Meiling Wang

    IPC: F21K9/237 ,  F21V17/18

    Abstract: The present invention disclosed an LED light source lampshade with a self-locking and pre-tightening device, which relates to the field of illuminating devices. The LED light source lampshade with a self-locking and pre-tightening device comprises a lampshade and a lamp body, wherein a side wall of the lampshade comprises an outer side wall of the lampshade and a plurality of connecting ribs, wherein a gap is provided between every two adjacent connecting ribs, wherein a limiting slot is provided between each connecting rib and the outer side wall of the lampshade, wherein a length of the connecting rib is greater than the length of the outer side wall of the lampshade, wherein a rotating boss is provided on an outer side surface of each of the plurality of connecting rib, so that the cross section of the side wall of the lampshade is in an approximately “concave” shape; the edge of the upper end surface of the lamp body is surrounded by a plurality of limiting slots, wherein a pre-tightening groove is provided between the adjacent two limiting ribs, wherein a self-locking groove is provided on one end of the pre-tightening groove near the guiding groove, wherein the lamp body is connected with the lampshade, wherein the rotating boss is matched with the pre-tightening groove. The LED light source lampshade with a self-locking and pre-tightening device provided by the present invention has advantages of simple structure, convenient installation and high production efficiency of the lampshade.

    Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture
    5.
    发明申请
    Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture 失效
    集成电路设计制造的分层随机分析过程优化

    公开(公告)号：US20080059143A1

    公开(公告)日：2008-03-06

    申请号：US11823601

    申请日：2007-06-27

    Applicant: Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

    Inventor： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

    IPC: G06F17/50

    CPC classification number: G06F17/5009 ,  G06F2217/10 ,  G06F2217/12 ,  G06F2217/62 ,  Y02P90/265

    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). A hierarchical SAP process breaks an overall circuit into a plurality of subcircuits and performs circuit simulation and SAP analysis steps on each subcircuit. An integration and reduction process combines the analysis results of each subcircuit, and a final SPICE/SAP process provides a model for the overall circuit based on the subcircuits.

    Abstract translation: 描述了结合随机分析过程（“SAP”）的集成电路设计工具。 SAP可以应用于许多级别的电路组件，包括晶体管器件，逻辑门器件和片上系统或芯片设计。 SAP通过使用少量采样点或角落的操作替代了大量传统的蒙特卡罗模拟。 SAP是使用模型拟合过程生成可以与任何数量的性能度量一起使用以产生性能变化预测以及相应的统计信息（例如，平均三西格玛概率等）的模型的分层方法。 分层SAP流程将整个电路分解成多个子电路，并在每个子电路上执行电路仿真和SAP分析步骤。 集成和减少流程结合了每个子电路的分析结果，最终的SPICE / SAP流程为基于子电路的整个电路提供了一个模型。

    Stochastic analysis process optimization for integrated circuit design and manufacture
    9.
    发明申请
    Stochastic analysis process optimization for integrated circuit design and manufacture 失效
    集成电路设计制造的随机分析过程优化

    公开(公告)号：US20060150129A1

    公开(公告)日：2006-07-06

    申请号：US11301999

    申请日：2005-12-12

    Applicant: Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

    Inventor： Hsien-Yen Chiu ,  Meiling Wang ,  Jun Li

    IPC: G06F17/50

    CPC classification number: G06F17/5022 ,  G06F2217/08

    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.

    Abstract translation: 描述了结合随机分析过程（“SAP”）的集成电路设计工具。 SAP可以应用于许多级别的电路组件，包括晶体管器件，逻辑门器件和片上系统或芯片设计。 SAP通过使用少量采样点或角落的操作替代了大量传统的蒙特卡罗模拟。 SAP是使用模型拟合过程生成可以与任何数量的性能度量一起使用以产生性能变化预测以及相应的统计信息（例如，平均三西格玛概率等）的模型的分层方法。 SAP提供了一种有效的方式来对由于全局参数（如器件尺寸，互连布线变化，经济变化和制造变化）引起的电路或系统变化进行建模。

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