公开(公告)号：US07569308B2

公开(公告)日：2009-08-04

申请号：US11065413

申请日：2005-02-24

申请人： Jun Wang ,  Alfred K. Wong ,  Edmund Y. Lam

发明人： Jun Wang ,  Alfred K. Wong ,  Edmund Y. Lam

IPC分类号： G03F9/00 ,  G03F7/20

CPC分类号： G03F7/70283 ,  G03F1/70 ,  G03F7/70466

摘要： An optical lithography method is disclosed that uses double exposure of a reusable template mask and a trim mask to fabricate regularly-placed rectangular contacts in standard cells of application-specific integrated circuits (ASICs). A first exposure of the reusable template mask with periodic patterns forms periodic dark lines on a wafer and a second exposure of an application-specific trim mask remove the unwanted part of the dark lines and the small cuts of the dark lines left form the rectangular regularly-placed contacts. All contacts are placed regularly in one direction while unrestrictedly in the perpendicular direction. The regular placement of patterns on the template mask enable more effective use of resolution enhancement technologies, which in turn allows a decrease in manufacturing cost and the minimum contact size and pitch. Since there is no extra application-specific mask needed comparing with the conventional lithography method for unrestrictedly-placed contacts, the extra cost is kept to the lowest. The method of the invention can be used in the fabrication of standard cells in application-specific integrated circuits (ASICs) to improve circuit performance and decrease circuit area and manufacturing cost.

摘要翻译： 公开了使用双重曝光的可重复使用的模板掩模和修剪掩模以在专用集成电路（ASIC）的标准单元中制造定向矩形触点的光学光刻方法。 具有周期性图案的可重复使用的模板掩模的第一次曝光在晶片上形成周期性的暗线，并且施加特定的修剪掩模的第二次曝光去除了暗线的不需要的部分，并且使黑色线的小切口形成矩形 放置联系人 所有触点在垂直方向上不受限制地沿着一个方向定期地放置。 在模板掩模上定期放置图案可以更有效地使用分辨率增强技术，从而可以降低制造成本和最小接触尺寸和间距。 由于与传统的无限制接触的光刻方法相比，不需要额外的应用特定掩模，所以额外的成本保持在最低水平。 本发明的方法可用于制造专用集成电路（ASIC）中的标准电池，以改善电路性能并降低电路面积和制造成本。

公开(公告)号：US06541166B2

公开(公告)日：2003-04-01

申请号：US09766005

申请日：2001-01-18

申请人： Scott M. Mansfield ,  Timothy A. Brunner ,  James A. Culp ,  Alfred K. Wong

发明人： Scott M. Mansfield ,  Timothy A. Brunner ,  James A. Culp ,  Alfred K. Wong

IPC分类号： G03F900

CPC分类号： G03F7/70433 ,  G03F1/70 ,  G03F7/70466 ,  H01J37/3026 ,  H01J2237/31761

摘要： The present invention relates generally to a method for lithographically printing a mask pattern on a substrate, in particular a semiconductor substrate, wherein the mask pattern includes features with diverse pitches. These features may include device features such as vias or contact holes and lines in integrated circuits. The method comprises splitting the mask pattern into a plurality of masks, wherein one or more of the masks contains relatively tightly nested features and one or more of the masks contains relatively isolated features. Each of the plurality of masks is then successively exposed on a photoresist layer on the substrate. For each exposure, the exposure conditions, photoresist layer, other thin films layers, etching process, mask writing process, and/or mask pattern bias may be optimized for the tightly nested feature pattern or isolated feature pattern.

公开(公告)号：US5932377A

公开(公告)日：1999-08-03

申请号：US28833

申请日：1998-02-24

申请人： Richard A. Ferguson ,  Lars W. Liebmann ,  Scott M. Mansfield ,  David S. O'Grady ,  Alfred K. Wong

发明人： Richard A. Ferguson ,  Lars W. Liebmann ,  Scott M. Mansfield ,  David S. O'Grady ,  Alfred K. Wong

IPC分类号： G03F1/30 ,  G03F9/00

CPC分类号： G03F1/30

摘要： A two-step method for eliminating transmission errors in alternating phase-shifting masks is described. Initially, the design data is selectively biased to provide a coarse reduction in the inherent transmission error between features of different phase, size, shape, and/or location. During fabrication of the mask with the modified data, residual transmission errors are then eliminated via the positioning of the edges of the etched-quartz trenches which define the phase of a given feature to a set location beneath the opaque chrome film. Application of feedback, in which the aerial image of the mask is monitored during the positioning of the etched-quartz edges, provides additional and precise control of the residual transmission error.

摘要翻译： 描述了用于消除交替移相掩模中的传输误差的两步法。 最初，设计数据被选择性地偏置以提供不同相位，大小，形状和/或位置的特征之间的固有传输误差的粗略减小。 在具有修改数据的掩模制造期间，通过将限定给定特征的相位的蚀刻石英沟槽的边缘定位到不透明铬膜下方的设定位置，残留透射误差被消除。 在蚀刻石英边缘的定位期间监测掩模的空中图像的反馈的应用提供对残留传输误差的附加且精确的控制。

公开(公告)号：US07155689B2

公开(公告)日：2006-12-26

申请号：US10680592

申请日：2003-10-07

申请人： Christophe Pierrat ,  Alfred K. Wong

发明人： Christophe Pierrat ,  Alfred K. Wong

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  G06F17/5068

摘要： Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.

摘要翻译： 与集成电路小型化相关的先进制造工艺和纳米尺度现象的小说暴露了设计规则的不足之处。 这种不足之处对于使用设计规则的集成电路创建流程的所有部分都有不利影响。 另外，深度亚微米制造所需的各种布局数据修改步骤的分离导致松弛和低效率。 本发明描述了通过使用可以补充或替代设计规则的制造过程和电路元件的统一模型来改进集成电路创建的方法。 通过捕获制造工艺和电路元件之间的相互依赖性，统一模型可实现有效的布局生成，从而形成更好的集成电路。

公开(公告)号：US07055127B2

公开(公告)日：2006-05-30

申请号：US10694474

申请日：2003-10-27

申请人： Christophe Pierrat ,  Alfred K. Wong

发明人： Christophe Pierrat ,  Alfred K. Wong

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F1/68

摘要： The manufacturing of integrated circuits relies on the use of optical proximity correction (OPC) to correct the printing of the features on the wafer. The data is subsequently fractured to accommodate the format of existing mask writer. The complexity of the correction after OPC can create some issues for vector-scan e-beam mask writing tools as very small slivers are created when the data is converted to the mask write tool format. Moreover the number of shapes created after fracturing is quite large and are not related to some important characteristics of the layout like for example critical areas. A new technique is proposed where the order of the OPC and fracturing steps is reversed. The fracturing step is done first in order to guarantee that no slivers are created and that the number of shapes is minimized. The shapes created can also follow the edges of critical zones so that critical and non-critical edges can be differentiated during the subsequent OPC step.

公开(公告)号：US06223139B1

公开(公告)日：2001-04-24

申请号：US09153842

申请日：1998-09-15

申请人： Alfred K. Wong ,  Richard A. Ferguson

发明人： Alfred K. Wong ,  Richard A. Ferguson

IPC分类号： G06F1750

CPC分类号： G03F7/705

摘要： A method of simulating aerial images of large mask areas obtained during the exposure step of a photo-lithographic process when fabricating a semiconductor integrated circuit silicon wafer is described. The method includes the steps of defining mask patterns to be projected by the exposure system to create images of the mask patterns; determining an appropriate sampling range and sampling interval; generating a characteristic matrix describing the exposure system; inverting the matrix to obtain eigenvalues as well as the eigenvectors (or kernels) representing the decomposition of the exposure system; convolving the mask patterns with these eigenvectors; and weighing the resulting convolution by the eigenvalues to form the aerial images. The method is characterized in that the characteristic matrix is precisely defined by the sampling range and the sampling interval, such that the sampling range is the shortest possible and the sampling interval, the largest possible, without sacrificing accuracy. The method of generating aerial images of patterns having large mask areas provides a speed improvement of several orders of magnitude over conventional approaches.

摘要翻译： 描述了在制造半导体集成电路硅晶片时模拟在光刻工艺的曝光步骤期间获得的大掩模区域的空间图像的方法。 该方法包括以下步骤：定义要由曝光系统投射的掩模图案以创建掩模图案的图像; 确定适当的采样范围和采样间隔; 生成描述曝光系统的特征矩阵; 反转矩阵以获得特征值以及表示曝光系统分解的特征向量（或内核）; 将掩模图案与这些特征向量进行卷积; 并通过特征值称量所得到的卷积以形成航空图像。 该方法的特征在于，特征矩阵由采样范围和采样间隔精确定义，使得采样范围尽可能最短，采样间隔最大，而不会牺牲精度。 产生具有大掩模区域的图案的空间图像的方法提供比传统方法几个数量级的速度改进。

公开(公告)号：US06602728B1

公开(公告)日：2003-08-05

申请号：US09754920

申请日：2001-01-05

申请人： Lars W. Liebmann ,  Scott Mansfield ,  Alfred K. Wong

发明人： Lars W. Liebmann ,  Scott Mansfield ,  Alfred K. Wong

IPC分类号： G01R3126

CPC分类号： G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/705

摘要： A method for generating an optical proximity correction (OPC) model includes generating a set of correction rules for a wafer design containing at least one of lines and assist features, determining a set of corrections that need to be made over a range of sizes and spaces of the lines and assist features based on the set of correction rules, and creating an optical proximity correction model for correcting the wafer design based on the set of corrections.

摘要翻译： 一种用于产生光学邻近校正（OPC）模型的方法包括为包含线和辅助特征中的至少一个的晶片设计生成一组校正规则，确定需要在一定范围的尺寸和空间上进行的一组校正 基于该组校正规则的线和辅助特征，以及基于该校正集创建用于校正晶片设计的光学邻近校正模型。

公开(公告)号：US06511791B1

公开(公告)日：2003-01-28

申请号：US09561469

申请日：2000-04-28

申请人： Scott J. Bukofsky ,  Gerhard Kunkel ,  Richard Wise ,  Alfred K. Wong

发明人： Scott J. Bukofsky ,  Gerhard Kunkel ,  Richard Wise ,  Alfred K. Wong

IPC分类号： G03F700

CPC分类号： G03F7/70466 ,  G03F7/203

摘要： A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed to form hollow polygonally-shaped clusters with a gap in the center. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure. Alternatively, the workpiece can be fully exposed first by stepping a series of full steps, then going back to the starting position, making a nanostep to reset the starting position and re-exposing from the reset starting position in the same way with full steps from the nanostepped position. The clusters may be in the shape of a hexagon or a diamond.

摘要翻译： 用于在双重曝光步骤和重复过程中曝光工件的方法通过形成掩模版掩模的设计而开始。 通过移除一些并列的特征来形成掩模版掩模的设计，以形成具有中心间隙的中空多边形簇。 在工件上形成未曝光的抗蚀剂。 将工件和掩模版掩模装入步进器。 通过掩模掩模将工件暴露。 用纳秒级重新定位工件。 然后在重新定位后将工件暴露在掩模版掩模之外。 测试多次曝光过程是否完成。 如果测试结果为“否”，则过程循环返回以重复上述步骤。 否则该过程已经完成。 通过单个标记的多次曝光产生重叠标记。 围绕阵列区域提供死区，其中在原始曝光中曝光之后发生印刷。 或者，可以通过步进一系列完整的步骤，然后返回到起始位置，首先完全暴露工件，从而使得纳秒能够以相同的方式从复位起始位置复位起始位置并再次曝光 纳米级位置。 簇可以是六边形或菱形的形状。

公开(公告)号：US06578190B2

公开(公告)日：2003-06-10

申请号：US09759013

申请日：2001-01-11

申请人： Richard A. Ferguson ,  Mark A. Lavin ,  Lars W. Liebmann ,  Alfred K. Wong

发明人： Richard A. Ferguson ,  Mark A. Lavin ,  Lars W. Liebmann ,  Alfred K. Wong

IPC分类号： G06F1750

CPC分类号： G03F1/70 ,  G03F1/36

摘要： A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

公开(公告)号：US06338922B1

公开(公告)日：2002-01-15

申请号：US09566885

申请日：2000-05-08

申请人： Lars W. Liebmann ,  Alfred K. Wong

发明人： Lars W. Liebmann ,  Alfred K. Wong

IPC分类号： G03F900

CPC分类号： G03F7/70425 ,  G03F1/30

摘要： A method for reducing lens aberrations sensitivity and proximity effects of alternating phase shifted masks is described. The critical features of a chip design layout are first identified. Multiple, narrow phase regions and auxiliary phase transitions, which provide additional opaque features, are then formed alongside the critical features such that a grating pattern of substantially uniform pitch is printed. Together with a complementary trim mask, the circuit pattern so delineated has reduced sensitivity to lens aberrations and proximity effects.

摘要翻译： 描述了用于减少交替相移掩模的透镜像差灵敏度和邻近效应的方法。 首先确定了芯片设计布局的关键特征。 然后，在临界特征旁边形成提供附加的不透明特征的多个窄相位区域和辅助相位转变，使得印刷基本均匀的间距的光栅图案。 与互补的修剪掩模一起，如此描绘的电路图案降低了对透镜像差和邻近效应的敏感性。