公开(公告)号：US08295479B2

公开(公告)日：2012-10-23

申请号：US12834247

申请日：2010-07-12

申请人： Dai Yamamoto ,  Jun Yajima ,  Kouichi Itoh

发明人： Dai Yamamoto ,  Jun Yajima ,  Kouichi Itoh

IPC分类号： H04L9/06

CPC分类号： H04L9/0625 ,  H04L2209/122 ,  H04L2209/125 ,  H04L2209/20 ,  H04L2209/24

摘要： In a MISTY1 FI function, an exclusive OR to which a round key KIij2 is inputted is arranged between an exclusive OR arranged on a 9-bit critical path in a first MISTY structure and a zero-extend conversion connected to the branching point of a 7-bit right system data path. Then, a 9-bit round key KIij1 is truncate-converted to seven bits, the exclusive OR of the seven bits and the round key KIij1 is calculated by an exclusive OR and the calculation result is inputted to an exclusive OR arranged on the right system data path in the second stage MISTY structure.

摘要翻译： 在MISTY1FF功能中，输入循环密钥KIij2的异或被布置在第一MISTY结构中的9位关键路径上的异或或连接到7的分支点的零扩展转换 右边的系统数据路径。 然后，9位循环密钥KIij1被截断转换为7位，通过异或来计算7位和循环密钥KIij1的异或，并将计算结果输入到排列在右系统上的异或 数据路径在第二阶段MISTY结构。

公开(公告)号：US08619975B2

公开(公告)日：2013-12-31

申请号：US12656018

申请日：2010-01-13

申请人： Dai Yamamoto ,  Kouichi Itoh ,  Jun Yajima

发明人： Dai Yamamoto ,  Kouichi Itoh ,  Jun Yajima

IPC分类号： H04L29/06 ,  G06F21/00

CPC分类号： H04L9/0625 ,  H04L2209/122

摘要： A cipher processing apparatus for arithmetic operations of an FO function and an FL function comprising: an FL function operating unit for generating a 2N-bit output based on a first extension key; a partial function operating unit for generating an N-bit output based on second and third extension keys; an N-bit intermediate register for storing an output of the partial operating unit; a 2N-bit first data register for storing data based on the output of the FL function operating unit; and a controller for making the partial function operating unit perform six cycles, inputting an output of the intermediate register to the FL function operating unit, and storing the data based on the output of the FL function operating unit in the first data register, in a first case in which the FL function uses a result of an arithmetic operation of the FO function.

摘要翻译： 一种用于FO功能和FL功能的算术运算的密码处理设备，包括：FL功能操作单元，用于基于第一扩展密钥产生2N位输出; 部分功能操作单元，用于基于第二和第三扩展密钥产生N位输出; N位中间寄存器，用于存储部分操作单元的输出; 一个2N位第一数据寄存器，用于根据FL功能操作单元的输出来存储数据; 以及用于使所述部分功能操作单元执行六个周期的控制器，将所述中间寄存器的输出输入到所述FL功能操作单元，并且基于所述FL功能操作单元的输出将所述数据存储在所述第一数据寄存器中， FL函数使用FO函数的算术运算结果的第一种情况。

公开(公告)号：US08335313B2

公开(公告)日：2012-12-18

申请号：US12834252

申请日：2010-07-12

申请人： Jun Yajima ,  Dai Yamamoto ,  Kouichi Itoh

发明人： Jun Yajima ,  Dai Yamamoto ,  Kouichi Itoh

IPC分类号： H04L9/06

CPC分类号： H04L9/0625 ,  H04L2209/122 ,  H04L2209/24 ,  H04L2209/805

摘要： When processing a data conversion function of a MISTY structure, such as the FO function of MISTY1, the logical calculation result t3 of the exclusive OR 614 of the process result of the FI function 602 of the MISTY structure in the second stage and a logical calculation result t1 of an exclusive OR 612 of the MISTY structure in the first stage is not stored in a register. The logical calculation result t3 and the logical calculation result of respective exclusive OR 642 and 643 are subject to a direct exclusive OR with the respective exclusive OR 642 and 643.

摘要翻译： 当处理诸如MISTY1的FO功能的MISTY结构的数据转换功能时，第二级的MISTY结构的FI功能602的处理结果的异或614的逻辑计算结果t3和逻辑计算 第一级的MISTY结构的异或612的结果t1不存储在寄存器中。 逻辑运算结果t3和各异或642和643的逻辑计算结果与各自的异或642和643进行直接异或运算。

公开(公告)号：US20100183144A1

公开(公告)日：2010-07-22

申请号：US12656018

申请日：2010-01-13

申请人： Dai Yamamoto ,  Kouichi Itoh ,  Jun Yajima

发明人： Dai Yamamoto ,  Kouichi Itoh ,  Jun Yajima

IPC分类号： H04L9/28

CPC分类号： H04L9/0625 ,  H04L2209/122

摘要： A cipher processing apparatus for arithmetic operations of an FO function and an FL function comprising: an FL function operating unit for generating a 2N-bit output based on a first extension key; a partial function operating unit for generating an N-bit output based on second and third extension keys; an N-bit intermediate register for storing an output of the partial operating unit; a 2N-bit first data register for storing data based on the output of the FL function operating unit; and a controller for making the partial function operating unit perform six cycles, inputting an output of the intermediate register to the FL function operating unit, and storing the data based on the output of the FL function operating unit in the first data register, in a first case in which the FL function uses a result of an arithmetic operation of the FO function.

摘要翻译： 一种用于FO功能和FL功能的算术运算的密码处理设备，包括：FL功能操作单元，用于基于第一扩展密钥产生2N位输出; 部分功能操作单元，用于基于第二和第三扩展密钥产生N位输出; N位中间寄存器，用于存储部分操作单元的输出; 一个2N位第一数据寄存器，用于根据FL功能操作单元的输出来存储数据; 以及用于使所述部分功能操作单元执行六个周期的控制器，将所述中间寄存器的输出输入到所述FL功能操作单元，并且基于所述FL功能操作单元的输出将所述数据存储在所述第一数据寄存器中， FL函数使用FO函数的算术运算结果的第一种情况。

公开(公告)号：US08422669B2

公开(公告)日：2013-04-16

申请号：US12891467

申请日：2010-09-27

申请人： Dai Yamamoto ,  Kouichi Itoh

发明人： Dai Yamamoto ,  Kouichi Itoh

IPC分类号： H04K1/00

CPC分类号： G06F7/725 ,  H04L9/003 ,  H04L9/3066

摘要： An apparatus includes a data storage to store a window table storing a table value with an index value mapped to the table value, the index value having same number of bits as a window width, the table value being a sum of a basic table value and a non-zero table correction value, the basic table value being obtained by multiplying a point G on an elliptic curve. An arithmetic processor generates the index value by reading from a scalar value at a bit position assigned to each bit of the window with the window being shifted, reads the table value from the window table according to the index value, and performs a doubling operation and an addition operation using the read table value. A corrector performs a correction on arithmetic results with a specific correction value responsive to the table correction value.

摘要翻译： 一种装置，包括：数据存储器，用于存储存储具有映射到表格值的索引值的表格值的窗口表，所述索引值具有与窗口宽度相同的位数，所述表格值是基本表格值和 非零表校正值，通过将点G乘以椭圆曲线获得的基本表值。 算术处理器通过从分配给窗口移位的窗口的每个位的位位置的标量值读取生成索引值，根据索引值从窗口表读取表格值，并执行加倍操作，并且 使用读表值的加法运算。 校正器根据表校正值对具有特定校正值的算术结果进行校正。

公开(公告)号：US08111827B2

公开(公告)日：2012-02-07

申请号：US12612290

申请日：2009-11-04

申请人： Dai Yamamoto ,  Kouichi Itoh

发明人： Dai Yamamoto ,  Kouichi Itoh

IPC分类号： H04K1/00 ,  H04K1/04 ,  H04K1/06 ,  H04L9/00 ,  H04L9/28

CPC分类号： H04L9/0625 ,  H04L2209/122

摘要： A cryptographic processing apparatus for performing arithmetic operation on an FL function and an FL−1 function in a cryptographic process includes a first arithmetic gate is configured to receive a first input bit string and a first extended key bit string, a first XOR gate configured to receive an output of the first arithmetic gate and a second input bit string, a second arithmetic gate configured to receive an output of the first XOR gate and a second extended key bit string, a second XOR gate configured to receive an output of the second arithmetic gate and the first input bit string, a third arithmetic gate configured to receive an output of the second XOR gate and the first extended key bit string, and a third XOR gate configured to receive an output of the third arithmetic gate and an output of the first XOR gate.

摘要翻译： 一种用于在密码处理中对FL功能和FL-1功能进行算术运算的加密处理装置，包括：第一运算门，被配置为接收第一输入位串和第一扩展密钥位串，第一XOR门被配置为 接收第一算术门和第二输入比特串的输出，第二运算门，被配置为接收第一异或门和第二扩展密钥位串的输出;第二异或门，被配置为接收第二算术的输出 栅极和第一输入位串，第三运算门，被配置为接收第二异或门和第一扩展密钥位串的输出;以及第三异或门，被配置为接收第三运算门的输出， 第一个XOR门。

公开(公告)号：US20100232601A1

公开(公告)日：2010-09-16

申请号：US12688033

申请日：2010-01-15

申请人： Kouichi ITOH ,  Dai Yamamoto ,  Tetsuya Izu ,  Masahiko Takenaka ,  Kazuyoshi Furukawa

发明人： Kouichi ITOH ,  Dai Yamamoto ,  Tetsuya Izu ,  Masahiko Takenaka ,  Kazuyoshi Furukawa

IPC分类号： H04L9/28

CPC分类号： G06F7/725 ,  G06F2207/7271

摘要： An apparatus for executing cryptographic calculation on the basis of an elliptic point on an elliptic curve includes: a memory for storing a first value including a plurality of digits; and a processor for executing a process including: obtaining a second value representing a point on the elliptic curve; calculating output values by using a predetermined equation, each digit of the first value, and the second value; determining whether at least one of the second value and the output values indicates a point of infinity; terminating the calculation when at least one of the second value and the output values indicates the point at infinity; and completing calculation when both the second value and the output values do not indicate the point at infinity, so as to obtain a result of the cryptographic calculation.

摘要翻译： 一种用于基于椭圆曲线上的椭圆点执行加密计算的装置包括：存储器，用于存储包括多个数字的第一值; 以及用于执行处理的处理器，包括：获得表示所述椭圆曲线上的点的第二值; 通过使用预定方程，第一值的每个数字和第二值来计算输出值; 确定所述第二值和所述输出值中的至少一个是否指示无限点; 当所述第二值和所述输出值中的至少一个指示所述无限远点时终止所述计算; 并且当第二值和输出值都不表示无限远点时完成计算，以获得加密计算的结果。

公开(公告)号：US20110176673A1

公开(公告)日：2011-07-21

申请号：US13064460

申请日：2011-03-25

申请人： Dai Yamamoto ,  Kouichi Itoh ,  Masayoshi Isobe ,  Souichi Okada

发明人： Dai Yamamoto ,  Kouichi Itoh ,  Masayoshi Isobe ,  Souichi Okada

IPC分类号： H04L9/28

CPC分类号： H04L9/0643 ,  G09C1/00 ,  H04L2209/122

摘要： An encrypting apparatus includes a digest part using a SHA-2 algorithm of which a basic unit of operation is 32*Y (Y=1 or 2) bits. The digest part includes a shift register including a series of registers, and a predetermined number of adders performing an addition operation based on data stored in the shift register. The shift register includes a (32*Y)/X-bit register, where X=2k (k is an integer such that 1≦k≦4 when Y=1 and 1≦k≦5 when Y=2). Each of the adders has a data width of (32*Y)/X bits and performs the addition operation in each cycle in which the data stored in the shift register is shifted between the registers with the data width of (32*Y)/X bits.

摘要翻译： 加密装置包括使用SHA-2算法的摘要部分，其基本操作单元是32×Y（Y = 1或2）位。 摘要部分包括一个包括一系列寄存器的移位寄存器和一个预定数量的加法器，它们基于存储在移位寄存器中的数据执行加法运算。 移位寄存器包括一个（32 * Y）/ X位寄存器，其中X = 2k（k是当Y = 1和1＆nlE; k＆nlE; 5，当Y = 2时，1＆nlE; k＆nlE; 4的整数）。 每个加法器的数据宽度为（32×Y）/ X位，并且在存储在移位寄存器中的数据在数据宽度为（32 * Y）/ X位的寄存器之间移位的每个周期中执行相加操作， X位。

公开(公告)号：US09209452B2

公开(公告)日：2015-12-08

申请号：US13983205

申请日：2012-01-24

申请人： Dai Yamamoto ,  Shinsuke Matsuno ,  Yoshinao Tatebayashi ,  Norio Takami

发明人： Dai Yamamoto ,  Shinsuke Matsuno ,  Yoshinao Tatebayashi ,  Norio Takami

IPC分类号： H01M4/131 ,  H01M4/58 ,  H01M10/0525 ,  H01M4/1391 ,  H01M4/36 ,  H01M4/485 ,  H01M4/505 ,  H01M4/525 ,  H01M10/42 ,  H01M4/02

CPC分类号： H01M4/131 ,  H01M4/1391 ,  H01M4/366 ,  H01M4/485 ,  H01M4/505 ,  H01M4/525 ,  H01M4/5825 ,  H01M10/0525 ,  H01M2004/021 ,  H01M2010/4292 ,  Y02E60/122

摘要： A positive electrode material for non-aqueous electrolyte secondary batteries having high rate characteristics and high energy density, and a battery using the same are provided. The non-aqueous electrolyte secondary battery includes a positive electrode containing a positive electrode material, a conductive agent and a binder; a negative electrode; a separator; and a non-aqueous electrolyte, in which the positive electrode material contains core particles and a coating material that covers from 10% to 90% of the surfaces of the core particles, the core particles are formed of a compound represented by LiaMbPO4 (wherein M represents at least one element selected from Fe, Mn, Co and Ni, and satisfies the relations: 0

摘要翻译： 提供了一种具有高速率特性和高能量密度的非水电解质二次电池用正极材料和使用其的电池。 非水电解质二次电池包括含有正极材料，导电剂和粘合剂的正极; 负极; 分隔符 和非水电解质，其中正极材料含有芯颗粒和覆盖芯颗粒表面的10％至90％的涂层材料，芯颗粒由LiaMbPO4表示的化合物（其中M 表示选自Fe，Mn，Co和Ni中的至少一种元素，满足关系：0

公开(公告)号：US20130302686A1

公开(公告)日：2013-11-14

申请号：US13983205

申请日：2012-01-24

申请人： Dai Yamamoto ,  Shinsuke Matsuno ,  Yoshinao Tatebayashi ,  Norio Takami

发明人： Dai Yamamoto ,  Shinsuke Matsuno ,  Yoshinao Tatebayashi ,  Norio Takami

IPC分类号： H01M4/131

CPC分类号： H01M4/131 ,  H01M4/1391 ,  H01M4/366 ,  H01M4/485 ,  H01M4/505 ,  H01M4/525 ,  H01M4/5825 ,  H01M10/0525 ,  H01M2004/021 ,  H01M2010/4292 ,  Y02E60/122

摘要： A positive electrode material for non-aqueous electrolyte secondary batteries having high rate characteristics and high energy density, and a battery using the same are provided. The non-aqueous electrolyte secondary battery includes a positive electrode containing a positive electrode material, a conductive agent and a binder; a negative electrode; a separator; and a non-aqueous electrolyte, in which the positive electrode material contains core particles and a coating material that covers from 10% to 90% of the surfaces of the core particles, the core particles are formed of a compound represented by LiaMbPO4 (wherein M represents at least one element selected from Fe, Mn, Co and Ni, and satisfies the relations: 0

摘要翻译： 提供了一种具有高速率特性和高能量密度的非水电解质二次电池用正极材料和使用其的电池。 非水电解质二次电池包括含有正极材料，导电剂和粘合剂的正极; 负极; 分隔符 和非水电解质，其中正极材料含有芯颗粒和覆盖芯颗粒表面的10％至90％的涂层材料，芯颗粒由LiaMbPO4表示的化合物（其中M 表示选自Fe，Mn，Co和Ni中的至少一种元素，并且满足关系：0