公开(公告)号：US20090065837A1

公开(公告)日：2009-03-12

申请号：US12264490

申请日：2008-11-04

Applicant: Jung-Hwa LEE ,  Si-Woo LEE

Inventor： Jung-Hwa LEE ,  Si-Woo LEE

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/0629 ,  H01L28/40

Abstract: Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.

Abstract translation: 提供了具有外围电路电容器的半导体存储器件。 在半导体存储器件中，第一节点电连接到外围电路区域中的多个电容器的多个下电极，以平行地连接至少一部分电容器。 第二节点电连接到外围电路区域中的电容器的多个上电极，以平行地连接至少一部分电容器。 第一节点形成在与单元阵列区域中的位线基本相同的电平上，并且由用于形成位线的相同材料形成。