公开(公告)号：US20120045284A1

公开(公告)日：2012-02-23

申请号：US12940385

申请日：2010-11-05

Applicant: Jae-Gon KIM ,  Jung-Hwa LEE ,  Yong-Chan CHO ,  Joo-Sung AHN ,  Choon-Oh LEE ,  Ho-Cheol SONG

Inventor： Jae-Gon KIM ,  Jung-Hwa LEE ,  Yong-Chan CHO ,  Joo-Sung AHN ,  Choon-Oh LEE ,  Ho-Cheol SONG

IPC: B09C1/08

CPC classification number: B09C1/02 ,  B09C1/08

Abstract: Provided is a method for remediating arsenic-contaminated soil, including: a collection step of collecting arsenic-contaminated soil; a washing step of adding the collected soil to a washing solution, which is acidic in nature and provides reducing conditions to the soil, so as to remove arsenic from the soil and transfer the removed arsenic to the washing solution; a solid-liquid separation step of separating the soil and the washing solution from each other after the washing step; and a post-treatment step of removing arsenic from the washing solution, which was separated in the solid-liquid separation step, and employing the soil for remediation.

Abstract translation: 提供了一种补救砷污染土壤的方法，包括：收集砷污染土壤的收集步骤; 将收集的土壤添加到本质上是酸性并为土壤提供还原条件的洗涤溶液的洗涤步骤，以从土壤中除去砷并将去除的砷转移到洗涤溶液中; 在洗涤步骤之后将污物和洗涤液彼此分离的固液分离步骤; 以及从固液分离工序中分离的洗涤液中除去砷的后处理工序，并使用土壤进行修复。

公开(公告)号：US20110075499A1

公开(公告)日：2011-03-31

申请号：US12894246

申请日：2010-09-30

Applicant: Jae-Young LEE ,  Jung-Hwa LEE ,  Bong-Jin KANG

Inventor： Jae-Young LEE ,  Jung-Hwa LEE ,  Bong-Jin KANG

IPC: G11C7/06

CPC classification number: G11C11/4091 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

Abstract: A semiconductor memory device comprises a substrate comprising a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region that are arranged in order from a first side to a second side. First and second bit lines are coupled to a plurality of memory cells in the first cell array region, and first and second complementary bit lines are coupled to a plurality of memory cells in the second cell array region. A first column selector is formed in the first sense circuit region and is coupled to the first bit line and the first complementary bit line. A second column selector is formed in the second sense circuit region and is coupled to the second bit line and the second complementary bit line. The first column selector and the second column selector are formed directly adjacent to each other.

Abstract translation: 一种半导体存储器件，包括一个衬底，该衬底包括从第一侧到第二侧依次布置的第一单元阵列区，第一感测电路区，第二感测电路区和第二单元阵列区。 第一和第二位线耦合到第一单元阵列区域中的多个存储单元，并且第一和第二互补位线耦合到第二单元阵列区域中的多个存储单元。 第一列选择器形成在第一感测电路区域中，并且耦合到第一位线和第一互补位线。 第二列选择器形成在第二感测电路区域中，并且耦合到第二位线和第二互补位线。 第一列选择器和第二列选择器彼此直接相邻地形成。

公开(公告)号：US07462912B2

公开(公告)日：2008-12-09

申请号：US11361580

申请日：2006-02-24

Applicant: Soon-Hong Ahn ,  Jung-Hwa Lee

Inventor： Soon-Hong Ahn ,  Jung-Hwa Lee

IPC: H01L29/76 ,  H01L29/00

CPC classification number: H01L27/0207 ,  H01L27/10894

Abstract: Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each other in parallel by using a conductive layer that is simultaneously formed with the self-align contact in a cell array region. Herein, the conductive layer and the self-align contact may be made of the same material. It is possible to embody the decoupling capacitor of a single stage cell type by connecting the conductive layer to a top interconnection layer. In addition, other embodiments implement the decoupling capacitor in a two-stage cell type by connecting a plurality of decoupling capacitors in series by means of the conductive layer in the peripheral circuit region.

Abstract translation: 提供了一种使用布局方案的半导体存储器件，其中同时形成有自对准接触的外围电路区域中的底部导电层连接到功率去耦电容器的一个电极。 通过使用与单元阵列区域中的自对准接触同时形成的导电层，并联地将多个电容器中选择的预定电容器并联连接。 这里，导电层和自对准接触可以由相同的材料制成。 通过将导电层连接到顶部互连层，可以体现单级电池类型的去耦电容器。 此外，其他实施例通过在外围电路区域中通过导电层连接多个解耦电容器来实现两级单元类型的去耦电容器。

公开(公告)号：US20080192535A1

公开(公告)日：2008-08-14

申请号：US12068983

申请日：2008-02-14

Applicant: Whee-jin Kwon ,  Jung-hwa Lee

Inventor： Whee-jin Kwon ,  Jung-hwa Lee

IPC: G11C11/34 ,  G11C7/00

CPC classification number: G11C7/065 ,  G11C7/12 ,  H01L27/0207 ,  H01L27/11803 ,  H01L29/66621

Abstract: A sense amplifier includes a first transistor having a gate electrode electrically connected to a bit line and a first electrode electrically connected to a complementary bit line. A second transistor has a gate electrode electrically connected to the complementary bit line and a first electrode electrically connected to the bit line. An equalizing transistor is disposed between the gate electrode of the first transistor and the gate electrode of the second transistor. The first electrode of the first transistor and a first electrode of the equalizing transistor are electrically connected to each other, and the first electrode of the second transistor and a second electrode of the equalizing transistor are electrically connected to each other.

Abstract translation: 读出放大器包括：第一晶体管，其具有电连接到位线的栅电极和与互补位线电连接的第一电极。 第二晶体管具有电连接到互补位线的栅电极和电连接到位线的第一电极。 在第一晶体管的栅电极和第二晶体管的栅电极之间设置均衡晶体管。 第一晶体管的第一电极和均衡晶体管的第一电极彼此电连接，并且第二晶体管的第一电极和均衡晶体管的第二电极彼此电连接。

公开(公告)号：US20080068069A1

公开(公告)日：2008-03-20

申请号：US11858071

申请日：2007-09-19

Applicant: Dong-Myung EUN ,  Jung-Hwa LEE

Inventor： Dong-Myung EUN ,  Jung-Hwa LEE

IPC: G05F1/10

CPC classification number: H02M3/07

Abstract: A high voltage generator is provided. The high voltage generator may comprise a high voltage output node, a plurality of pumping stages, a plurality of charge transfer elements, and a field relieving unit. The plurality of pumping stages sequentially pump charges in response to a sequentially enabled plurality of pump signals and output the pumped charges, respectively. The plurality of charge transfer elements sequentially transfer the charges sequentially pumped by the plurality of pumping stages to the next pumping stage and transfer the charge of an output node of the last pumping stage to the high voltage output node. The field relieving unit reduces the voltage of the input terminal of at least one of the plurality of charge transfer elements. The high voltage generator reduces hot carrier injection in charge transfer transistors without decreasing pumping efficiency.

Abstract translation: 提供高压发生器。 高压发生器可以包括高压输出节点，多个泵送级，多个电荷转移元件和场释放单元。 多个泵送阶段响应于顺序启用的多个泵浦信号顺序地泵送电荷并分别输出泵送的电荷。 多个电荷转移元件顺序地将由多个泵送阶段泵浦的电荷转移到下一个泵送级，并将最后一个泵浦级的输出节点的电荷传送到高电压输出节点。 场释放单元降低多个电荷转移元件中的至少一个的输入端子的电压。 高压发生器减少电荷转移晶体管中的热载流子注入，而不会降低泵送效率。

公开(公告)号：US20070153612A1

公开(公告)日：2007-07-05

申请号：US11640857

申请日：2006-12-19

Applicant: Jae-Young Lee ,  Hong-Jun Lee ,  Jung-Hwa Lee

Inventor： Jae-Young Lee ,  Hong-Jun Lee ,  Jung-Hwa Lee

IPC: G11C5/14

CPC classification number: G11C5/145

Abstract: A circuit generates a boosted voltage in a semiconductor memory device, where the semiconductor memory device includes a memory cell array having a plurality of non-edge sub-arrays and at least one edge sub-array. The circuit includes a plurality of boosted voltage generators configured to generate a boosted voltage having different current driving capabilities to activate the non-edge sub-arrays and the edge sub-arrays and to supply the boosted voltage to the memory cell array.

Abstract translation: 电路在半导体存储器件中产生升压电压，其中半导体存储器件包括具有多个非边缘子阵列和至少一个边缘子阵列的存储单元阵列。 该电路包括多个升压电压发生器，其被配置为产生具有不同电流驱动能力的升压电压以激活非边缘子阵列和边缘子阵列，并将升压电压提供给存储单元阵列。

公开(公告)号：US20060289932A1

公开(公告)日：2006-12-28

申请号：US11361580

申请日：2006-02-24

Applicant: Soon-Hong Ahn ,  Jung-Hwa Lee

Inventor： Soon-Hong Ahn ,  Jung-Hwa Lee

IPC: H01L29/76

CPC classification number: H01L27/0207 ,  H01L27/10894

Abstract: Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each other in parallel by using a conductive layer that is simultaneously formed with the self-align contact in a cell array region. Herein, the conductive layer and the self-align contact may be made of the same material. It is possible to embody the decoupling capacitor of a single stage cell type by connecting the conductive layer to a top interconnection layer. In addition, other embodiments implement the decoupling capacitor in a two-stage cell type by connecting a plurality of decoupling capacitors in series by means of the conductive layer in the peripheral circuit region.

Abstract translation: 提供了一种使用布局方案的半导体存储器件，其中同时形成有自对准接触的外围电路区域中的底部导电层连接到功率去耦电容器的一个电极。 通过使用与单元阵列区域中的自对准接触同时形成的导电层，并联地将多个电容器中选择的预定电容器并联连接。 这里，导电层和自对准接触可以由相同的材料制成。 通过将导电层连接到顶部互连层，可以体现单级电池类型的去耦电容器。 此外，其他实施例通过在外围电路区域中通过导电层连接多个解耦电容器来实现两级单元类型的去耦电容器。

公开(公告)号：US5657265A

公开(公告)日：1997-08-12

申请号：US673001

申请日：1996-07-01

Applicant: Jei-Hwan Yoo ,  Jung-Hwa Lee

Inventor： Jei-Hwan Yoo ,  Jung-Hwa Lee

IPC: G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/06

CPC classification number: G11C7/10 ,  G11C11/4096

Abstract: A semiconductor memory device includes at least four memory cell array blocks, each having an array of memory cells, row and column decoders for selecting a memory cell designated by a row and column address, an I/O line for inputting/outputting data of the memory cell array block, and an I/O driver connected to the I/O line for selectively driving data to/from a selected memory cell. A first data line transmits the data, being connected between the I/O driver of one memory cell array block and the I/O driver of another memory cell array block oppositely arranged with respect to a central portion of the semiconductor memory device. A second data line transmits the data by connecting the first data lines of at least two memory cell array blocks disposed adjacent to each other. A data sense amplifier, connected to the second data line, senses and amplifies the data, and a data output unit, connected to the data sense amplifier, outputs the amplified data to an external lead frame. Therefore, the present invention has an advantage in that a relatively small layout area in required and a relatively low amount of power is consumed.

Abstract translation: 半导体存储器件包括至少四个存储单元阵列块，每个存储单元阵列块具有存储单元阵列，用于选择由行和列地址指定的存储单元的行和列解码器，用于输入/输出数据的数据的I / O线 存储单元阵列块和连接到I / O线的I / O驱动器，用于选择性地将数据传送到所选择的存储单元。 第一数据线传送连接在一个存储单元阵列块的I / O驱动器和相对于半导体存储器件的中心部分相对布置的另一存储单元阵列块的I / O驱动器之间的数据。 第二数据线通过连接彼此相邻布置的至少两个存储单元阵列块的第一数据线来发送数据。 连接到第二数据线的数据读出放大器感测并放大数据，连接到数据读出放大器的数据输出单元将放大的数据输出到外部引线框。 因此，本发明的优点是消耗了所需的相对小的布局面积和相对低的功率。

公开(公告)号：US08475080B2

公开(公告)日：2013-07-02

申请号：US12940385

申请日：2010-11-05

Applicant: Jae-Gon Kim ,  Jung-Hwa Lee ,  Yong-Chan Cho ,  Joo-Sung Ahn ,  Choon-Oh Lee ,  Ho-Cheol Song

Inventor： Jae-Gon Kim ,  Jung-Hwa Lee ,  Yong-Chan Cho ,  Joo-Sung Ahn ,  Choon-Oh Lee ,  Ho-Cheol Song

IPC: B09C1/02

CPC classification number: B09C1/02 ,  B09C1/08

Abstract: Provided is a method for remediating arsenic-contaminated soil, including: a collection step of collecting arsenic-contaminated soil; a washing step of adding the collected soil to a washing solution, which is acidic in nature and provides reducing conditions to the soil, so as to remove arsenic from the soil and transfer the removed arsenic to the washing solution; a solid-liquid separation step of separating the soil and the washing solution from each other after the washing step; and a post-treatment step of removing arsenic from the washing solution, which was separated in the solid-liquid separation step, and employing the soil for remediation.

Abstract translation: 提供了一种补救砷污染土壤的方法，包括：收集砷污染土壤的收集步骤; 将收集的土壤添加到本质上是酸性并为土壤提供还原条件的洗涤溶液的洗涤步骤，以从土壤中除去砷并将去除的砷转移到洗涤溶液中; 在洗涤步骤之后将污物和洗涤液彼此分离的固液分离步骤; 以及从固液分离工序中分离的洗涤液中除去砷的后处理工序，并使用土壤进行修复。

公开(公告)号：US08232070B2

公开(公告)日：2012-07-31

申请号：US12532267

申请日：2007-03-30

Applicant: Hyun Sook Lee ,  Jung Hwa Lee

Inventor： Hyun Sook Lee ,  Jung Hwa Lee

IPC: G01N33/574

CPC classification number: C12Q1/6886 ,  C12Q2600/136 ,  C12Q2600/158 ,  G01N33/5011 ,  G01N2333/4748

Abstract: This invention relates to a gene encoding ΔNp63α and screening methods of anticancer-drugs thereof, more specifically a gene encoding ΔNp63α and a protein which is transported from nucleus to cytoplasm by contacting with potential anti-cancer-drugs in an epithelial cell carcinoma, a recombinant vector comprising said gene and reporter genes, and carcinoma cells comprising said vector. Also, This invention relates to high throughput screening methods of anticancer-drug comprising identifying the transportation of ΔNp63α protein from nucleus to cytoplasm by contacting with potential anticancer-drug in a carcinoma cell.

Abstract translation: 本发明涉及一种编码“Dgr;Np63α”的基因及其抗癌药的筛选方法，更具体地说，一种编码“Dgr;Np63α”的基因和通过与上皮细胞中的潜在抗癌药物接触从细胞核转运至细胞质的蛋白质 癌，包含所述基因和报告基因的重组载体，以及包含所述载体的癌细胞。 此外，本发明涉及抗癌药物的高通量筛选方法，包括通过与癌细胞中的潜在抗癌药物接触来鉴定从细胞核到细胞质的转运和转运Np63α蛋白。