中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.014 seconds)

    DIAGNOSIS SYSTEM OF DEFICIENT AND FORCEFUL PULSE
    3.
    发明申请
    DIAGNOSIS SYSTEM OF DEFICIENT AND FORCEFUL PULSE 有权
    缺陷和有力脉搏诊断系统

    公开(公告)号：US20100022895A1

    公开(公告)日：2010-01-28

    申请号：US12531246

    申请日：2007-09-28

    Applicant: Jong Yeol Kim ,  Jeon Lee ,  Yu Jung Lee ,  Si Woo Lee ,  Jaehwan Kang ,  Hyunhee Ryu ,  Hae-Jung Lee ,  Eun-Ji Choi

    Inventor： Jong Yeol Kim ,  Jeon Lee ,  Yu Jung Lee ,  Si Woo Lee ,  Jaehwan Kang ,  Hyunhee Ryu ,  Hae-Jung Lee ,  Eun-Ji Choi

    IPC: A61B5/021 ,  A61B5/02

    CPC classification number: A61B5/024 ,  A61B5/4854 ,  A61B5/6824 ,  A61B2562/0247 ,  A61B2562/046 ,  G06F19/00

    Abstract: Disclosed herein is a system for diagnosing a deficient pulse and an forceful pulse. The system includes a pulse diagnotic device, a deficient pulse and forceful pulse determining device, and an output device. The pulse diagnotic device measures pulse condition information at an examinee's Cun (˜\f˜) Gu (H), and Chi (,R) pulse-taking locations on his or her wrist using one or more pulse-taking sensors. The deficient pulse and forceful pulse determining device is operably connected to the pulse diagnotic device, analyzes the pulse pressure information measured by the pulse diagnotic device, calculates a quantified deficiency/forceful coefficient, and determines whether a pulse of interest is a deficient pulse or an forceful pulse. The output device is connected to the determining device and displays results of the determination.

    Abstract translation: 本文公开了一种用于诊断缺陷脉冲和有力脉冲的系统。 该系统包括脉冲诊断装置，缺陷脉冲和有力的脉冲确定装置，以及输出装置。 脉冲诊断装置使用一个或多个脉冲采集传感器来测量他或她的手腕上的受检者Cun（〜\ f〜）Gu（H）和Chi（，R）脉搏取得位置的脉搏状况信息。 脉冲和有力的脉冲确定装置可操作地连接到脉冲诊断装置，分析由脉冲诊断装置测量的脉搏压力信息，计算定量不足/有力系数，并确定感兴趣的脉冲是否是缺陷脉冲 有力的脉搏 输出设备连接到确定设备并显示确定的结果。

    Diagnosis system of deficient and forceful pulse
    4.
    发明授权
    Diagnosis system of deficient and forceful pulse 有权
    缺乏有力脉搏的诊断系统

    公开(公告)号：US08317716B2

    公开(公告)日：2012-11-27

    申请号：US12531246

    申请日：2007-09-28

    Applicant: Jong Yeol Kim ,  Jeon Lee ,  Yu Jung Lee ,  Si Woo Lee ,  Jaehwan Kang ,  Hyunhee Ryu ,  Hae-Jung Lee ,  Eun-Ji Choi

    Inventor： Jong Yeol Kim ,  Jeon Lee ,  Yu Jung Lee ,  Si Woo Lee ,  Jaehwan Kang ,  Hyunhee Ryu ,  Hae-Jung Lee ,  Eun-Ji Choi

    IPC: A61B5/02

    CPC classification number: A61B5/024 ,  A61B5/4854 ,  A61B5/6824 ,  A61B2562/0247 ,  A61B2562/046 ,  G06F19/00

    Abstract: Disclosed herein is a system for diagnosing a deficient pulse and an forceful pulse. The system includes a pulse diagnotic device, a deficient pulse and forceful pulse determining device, and an output device. The pulse diagnotic device measures pulse condition information at an examinee's Cun (˜\f˜) Gu (H), and Chi (,R) pulse-taking locations on his or her wrist using one or more pulse-taking sensors. The deficient pulse and forceful pulse determining device is operably connected to the pulse diagnotic device, analyzes the pulse pressure information measured by the pulse diagnotic device, calculates a quantified deficiency/forceful coefficient, and determines whether a pulse of interest is a deficient pulse or an forceful pulse. The output device is connected to the determining device and displays results of the determination.

    Abstract translation: 本文公开了一种用于诊断缺陷脉冲和有力脉冲的系统。 该系统包括脉冲诊断装置，缺陷脉冲和有力的脉冲确定装置，以及输出装置。 脉冲诊断装置使用一个或多个脉冲采集传感器来测量他或她的手腕上的受检者的Cun（〜\ f〜）Gu（H）和Chi（，R）脉搏取得位置的脉搏状况信息。 脉冲和有力的脉冲确定装置可操作地连接到脉冲诊断装置，分析由脉冲诊断装置测量的脉搏压力信息，计算定量不足/有力系数，并确定感兴趣的脉冲是否是缺陷脉冲 有力的脉搏 输出设备连接到确定设备并显示确定的结果。

    Semiconductor memory device having capacitor for peripheral circuit
    5.
    发明授权
    Semiconductor memory device having capacitor for peripheral circuit 失效
    具有用于外围电路的电容器的半导体存储器件

    公开(公告)号：US07999299B2

    公开(公告)日：2011-08-16

    申请号：US12264490

    申请日：2008-11-04

    Applicant: Jung-Hwa Lee ,  Si-Woo Lee

    Inventor： Jung-Hwa Lee ,  Si-Woo Lee

    IPC: H01L27/108

    CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/0629 ,  H01L28/40

    Abstract: Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.

    Abstract translation: 提供了具有外围电路电容器的半导体存储器件。 在半导体存储器件中，第一节点电连接到外围电路区域中的多个电容器的多个下电极，以平行地连接至少一部分电容器。 第二节点电连接到外围电路区域中的电容器的多个上电极，以平行地连接至少一部分电容器。 第一节点形成在与单元阵列区域中的位线基本相同的电平上，并且由用于形成位线的相同材料形成。

    Semiconductor device for preventing inflow of high current from an input/output pad and a circuit for preventing inflow of high current thereof
    8.
    发明授权
    Semiconductor device for preventing inflow of high current from an input/output pad and a circuit for preventing inflow of high current thereof 失效
    用于防止从输入/输出焊盘流入高电流的半导体装置和用于防止高电流流入的电路

    公开(公告)号：US07667330B2

    公开(公告)日：2010-02-23

    申请号：US12208200

    申请日：2008-09-10

    Applicant: Si Woo Lee

    Inventor： Si Woo Lee

    IPC: H01L29/40

    CPC classification number: H01L23/522 ,  H01L23/585 ,  H01L23/60 ,  H01L24/05 ,  H01L27/0288 ,  H01L2924/14

    Abstract: A semiconductor device includes an input/output pad, an input line of an internal circuit, and a plurality of metal lines formed on a lower portion of the input/output pad to have a buffer area overlapping with a plane area of the input/output pad, wherein one of an entirety and a portion of the plurality of metal lines included in the buffer area forms protective resistance interconnecting the input/output pad to the input line.

    Abstract translation: 半导体器件包括输入/​​输出焊盘，内部电路的输入线和形成在输入/输出焊盘的下部上的多条金属线，以具有与输入/输出的平面区域重叠的缓冲区域 衬垫，其中包括在缓冲区域中的多个金属线的整体和一部分中的一个形成将输入/输出焊盘互连到输入线的保护电阻。

    Remote control system and method for setting up and simulcasting carrier frequencies
    9.
    发明申请
    Remote control system and method for setting up and simulcasting carrier frequencies 审中-公开
    用于建立和同步播送载波频率的遥控系统和方法

    公开(公告)号：US20070069919A1

    公开(公告)日：2007-03-29

    申请号：US11480531

    申请日：2006-07-05

    Applicant: Si-Woo Lee

    Inventor： Si-Woo Lee

    IPC: G05B19/02 ,  G08C19/12

    CPC classification number: G08C23/04

    Abstract: In a remote control system and a method for setting up and simulcasting carrier frequencies, a carrier frequency is set up according to a carrier frequency setup signal inputted by a user, and digital data of a signal corresponding to a button pushed by a user for controlling a remote control receiver are modulated onto the setup carrier frequency, and the modulated digital data are sent out.

    Abstract translation: 在遥控系统和用于建立和同步播放载波频率的方法中，根据由用户输入的载波频率设置信号建立载波频率，以及与由用户控制的按钮相对应的信号的数字数据 遥控接收机被调制到建立载波频率上，调制的数字数据被发送出去。

    Multilayer passivation process for forming air gaps within a dielectric between interconnections
    10.
    发明授权
    Multilayer passivation process for forming air gaps within a dielectric between interconnections 有权
    用于在互连之间的电介质内形成气隙的多层钝化工艺

    公开(公告)号：US06399476B2

    公开(公告)日：2002-06-04

    申请号：US09432101

    申请日：1999-11-02

    Applicant: Jin Yang Kim ,  Si-Woo Lee ,  Won Seong Lee ,  Sang-Pil Sim

    Inventor： Jin Yang Kim ,  Si-Woo Lee ,  Won Seong Lee ,  Sang-Pil Sim

    IPC: H01C214763

    CPC classification number: H01L21/7682

    Abstract: A process for forming air gaps within an interlayer dielectric is provided to reduce loading capacitance between interconnections. A first dielectric layer is deposited on the spaced interconnections. This first dielectric layer is deposited more thickly at the top sides than at the bottom sides of the interconnections. A second dielectric layer is deposited on the first dielectric layer to a controlled thickness that causes formation of air gaps therewithin between the interconnections. The poor step coverage of the first dielectric layer makes it easier to form the air gaps. Air gaps between interconnections allows reduced permittivity of the overall dielectric structures and thereby reduces the interconnect line to line capacitance, and increases the possible operation speed of the semiconductor device.

    Abstract translation: 提供了一种用于在层间电介质内形成气隙的工艺，以减少互连之间的负载电容。 第一介电层沉积在间隔开的互连上。 该第一电介质层在顶侧比在互连的底侧更厚地沉积。 第二电介质层沉积在第一介电层上至受控的厚度，导致在互连之间形成空隙。 第一电介质层的差的台阶覆盖使得容易形成气隙。 互连之间的空气间隙允许整个电介质结构的介电常数降低，从而将互连线减少到线路电容，并且增加半导体器件的可能的操作速度。

Patent Agency Ranking