公开(公告)号：US07851354B2

公开(公告)日：2010-12-14

申请号：US12267785

申请日：2008-11-10

申请人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

发明人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

摘要翻译： 半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。 该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。 形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。 在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

公开(公告)号：US07462899B2

公开(公告)日：2008-12-09

申请号：US11354175

申请日：2006-02-15

申请人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

发明人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

IPC分类号： H01L27/108

CPC分类号： H01L21/76895 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

摘要翻译： 半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。 该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。 形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。 在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

公开(公告)号：US20060186479A1

公开(公告)日：2006-08-24

申请号：US11354175

申请日：2006-02-15

申请人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

发明人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

摘要翻译： 半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。 该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。 形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。 在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

公开(公告)号：US07326621B2

公开(公告)日：2008-02-05

申请号：US11015366

申请日：2004-12-16

申请人： Young-sun Cho ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Ji-hong Kim ,  Hong-Mi Park

发明人： Young-sun Cho ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Ji-hong Kim ,  Hong-Mi Park

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/823487 ,  H01L29/42376

摘要： A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

摘要翻译： 一种制造凹槽通道阵列晶体管的方法。 使用相对于硅衬底具有高蚀刻选择性的掩模层图案，蚀刻硅衬底和隔离绝缘层以形成凹槽沟道沟槽。 在凹槽沟道沟槽上形成栅极绝缘层和凹槽叠层之后，在与硅栅极叠层的两个侧壁相邻的硅衬底中形成源极和漏极，由此完成凹槽沟道阵列晶体管。 由于使用具有相对于硅衬底的高蚀刻选择性的掩模层图案，所以可以容易地控制凹槽沟槽的深度，同时获得硅衬底的良好蚀刻均匀性。

公开(公告)号：US20050136616A1

公开(公告)日：2005-06-23

申请号：US11015366

申请日：2004-12-16

申请人： Young-sun Cho ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Ji-hong Kim ,  Hong-Mi Park

发明人： Young-sun Cho ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Ji-hong Kim ,  Hong-Mi Park

IPC分类号： H01L21/3065 ,  H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/823487 ,  H01L29/42376

摘要： A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

摘要翻译： 一种制造凹槽通道阵列晶体管的方法。 使用相对于硅衬底具有高蚀刻选择性的掩模层图案，蚀刻硅衬底和隔离绝缘层以形成凹槽沟道沟槽。 在凹槽沟道沟槽上形成栅极绝缘层和凹槽叠层之后，在与硅栅极叠层的两个侧壁相邻的硅衬底中形成源极和漏极，从而完成凹槽沟道阵列晶体管。 由于使用具有相对于硅衬底的高蚀刻选择性的掩模层图案，所以可以容易地控制凹槽沟槽的深度，同时获得硅衬底的良好蚀刻均匀性。