公开(公告)号：US09817769B1

公开(公告)日：2017-11-14

申请号：US15483756

申请日：2017-04-10

Applicant: Juniper Networks, Inc.

Inventor： Xiangwen Xu ,  Hexin Wang ,  Xiang Zhu

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F12/109 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68

Abstract: In one embodiment, a method includes receive a translation vector, selecting a translation entry from a plurality of translation entries, and determining whether the translation entry is associated with a first identifier class or a second identifier class. The translation vector includes a first identifier, a second identifier, and a virtual memory identifier. The first identifier is associated with a first identifier class, and the second identifier is associated with a second identifier class. The translation vector is received from a translation module including a memory configured to store the plurality of translation entries. Each translation entry from the plurality of translation entries including a virtual memory identifier. The translation entry is selected from the plurality of translation entries of the translation module based on the virtual memory identifier of the translation vector. The determining whether the translation entry is associated with the first identifier class or the second identifier class is based on a shared indicator associated with the translation entry.

公开(公告)号：US09413645B1

公开(公告)日：2016-08-09

申请号：US14607569

申请日：2015-01-28

Applicant: Juniper Networks, Inc.

Inventor： Hexin Wang

IPC: H04L12/56 ,  H04L12/721 ,  H04L12/935 ,  H04L12/947

CPC classification number: H04L45/44 ,  H04L41/046 ,  H04L41/0853 ,  H04L49/25 ,  H04L49/30

Abstract: In some embodiments, a non-transitory processor-readable medium includes code to cause a processor to receive, at a network management module, a request for data plane information associated with a set of access switches of a distributed switch. The non-transitory processor-readable medium includes code to cause the processor to send, in response to the request, an instruction to each access switch from the set of access switches such that a proxy module at each access switch accesses data plane information at at least one line card at that access switch. The non-transitory processor-readable medium includes code to cause the processor to receive, from each access switch from the set of access switches, the data plane information associated with that access switch, and then send a signal to output, on a single interface, the data plane information associated with each access switch from the set of access switches.