公开(公告)号：US07131086B2

公开(公告)日：2006-10-31

申请号：US10915608

申请日：2004-08-11

申请人： Junya Yamasaki ,  Sumiko Maeda ,  Kenya Takeyama ,  Yukio Makino

发明人： Junya Yamasaki ,  Sumiko Maeda ,  Kenya Takeyama ,  Yukio Makino

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A logic verification device, a logic verification method and a logic verification computer program that can reduce the number of steps involved in designing a logic circuit particularly when the designed logic circuit is subjected to logic verification and modification at the spot where an error is detected. The logic verification device comprises a data converter section adapted to convert real circuit data to be processed for designing a logic circuit into data for verification to be processed for logic verification and vice versa, a verifier section adapted to operate for logic verification of said data for verification and a temporary modifier section adapted to acquire the result of verification of said verifier section and the modification candidate data corresponding to the result of verification of said verifier section and pre-selected as candidate data for modification of said data for verification and modify said data for verification on the basis of said acquired result of verification and said acquired modification candidate data.

摘要翻译： 逻辑验证装置，逻辑验证方法和逻辑验证计算机程序，可以减少在设计逻辑电路时涉及的步骤数，特别是当设计的逻辑电路在检测到错误的位置进行逻辑验证和修改时。 逻辑验证装置包括：数据转换器部分，适于将待处理的实际电路数据转换为用于设计逻辑电路的数据以进行逻辑验证处理以进行验证，反之亦然;验证器部分，适于操作所述数据的逻辑验证 验证和临时修改器部分，其适于获取所述验证器部分的验证结果和对应于所述验证​​器部分的验证结果的修改候选数据，并且被预先选择作为用于修改所述数据进行验证的候选数据，并修改所述数据 用于基于所述获取的验证结果和所述获取的修改候选数据进行验证。

公开(公告)号：US20050229122A1

公开(公告)日：2005-10-13

申请号：US10915608

申请日：2004-08-11

申请人： Junya Yamasaki ,  Sumiko Maeda ,  Kenya Takeyama ,  Yukio Makino

发明人： Junya Yamasaki ,  Sumiko Maeda ,  Kenya Takeyama ,  Yukio Makino

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A logic verification device, a logic verification method and a logic verification computer program that can reduce the number of steps involved in designing a logic circuit particularly when the designed logic circuit is subjected to logic verification and modification at the spot where an error is detected. The logic verification device comprises a data converter section adapted to convert real circuit data to be processed for designing a logic circuit into data for verification to be processed for logic verification and vice versa, a verifier section adapted to operate for logic verification of said data for verification and a temporary modifier section adapted to acquire the result of verification of said verifier section and the modification candidate data corresponding to the result of verification of said verifier section and pre-selected as candidate data for modification of said data for verification and modify said data for verification on the basis of said acquired result of verification and said acquired modification candidate data.

摘要翻译： 逻辑验证装置，逻辑验证方法和逻辑验证计算机程序，可以减少在设计逻辑电路时涉及的步骤数，特别是当设计的逻辑电路在检测到错误的位置进行逻辑验证和修改时。 逻辑验证装置包括：数据转换器部分，适于将待处理的实际电路数据转换为用于设计逻辑电路的数据以进行逻辑验证处理以进行验证，反之亦然;验证器部分，适于操作所述数据的逻辑验证 验证和临时修改器部分，其适于获取所述验证器部分的验证结果和对应于所述验证​​器部分的验证结果的修改候选数据，并且被预先选择作为用于修改所述数据进行验证的候选数据，并修改所述数据 用于基于所述获取的验证结果和所述获取的修改候选数据进行验证。

公开(公告)号：US5856925A

公开(公告)日：1999-01-05

申请号：US882754

申请日：1997-06-05

申请人： Sumiko Maeda ,  Hisataka Fukase

发明人： Sumiko Maeda ,  Hisataka Fukase

IPC分类号： G06F17/50 ,  G06F15/00

CPC分类号： G06F17/50 ,  G06F2217/74 ,  Y10S706/919 ,  Y10S706/921 ,  Y10S706/922

摘要： In a method for managing design data regarding an electronic circuit in order to design and analyze the electronic circuit, the design data is arranged according to a hierarchical-layer module structure. The design data in each of hierarchical layers of the hierarchical-layer module structure is divided into objects. The objects together for each of the hierarchical layers are connected together and the objects are connected together over the hierarchical layers. The design data including design data having different items and design data having different data lengths is integrally managed.

摘要翻译： 在用于管理关于电子电路的设计数据以便设计和分析电子电路的方法中，设计数据根据分级层模块结构来布置。 分级层模块结构的每层分层设计数据分为对象。 用于每个分级层的一起的对象被连接在一起，并且对象通过层次结构连接在一起。 包括具有不同项目的设计数据和具有不同数据长度的设计数据的设计数据被一体地管理。