公开(公告)号：US09653156B2

公开(公告)日：2017-05-16

申请号：US14712017

申请日：2015-05-14

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Masanobu Shirakawa ,  Tsuyoshi Atsumi ,  Hidetaka Tsuji ,  Tomoyuki Kantani ,  Hideaki Yamamoto ,  Yasuhiko Kurosawa

IPC分类号： G11C11/56 ,  G11C7/04

CPC分类号： G11C11/5642 ,  G11C7/04

摘要： According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.

公开(公告)号：US20160247561A1

公开(公告)日：2016-08-25

申请号：US14712017

申请日：2015-05-14

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Masanobu SHIRAKAWA ,  Tsuyoshi Atsumi ,  Hidetaka Tsuji ,  Tomoyuki Kantani ,  Hideaki Yamamoto ,  Yasuhiko Kurosawa

IPC分类号： G11C11/56

CPC分类号： G11C11/5642 ,  G11C7/04

摘要： According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.

摘要翻译： 根据一个实施例，存储器系统包括非易失性半导体存储器和存储器控制器。 存储器控制器具有第一信号生成部，其生成与用于非易失性半导体存储器的读取操作的读取电压相关的第一信号;第二信号生成部，其生成指定用于温度校正的温度系数的第二信号 以及第一接口部分，其输出第一信号，第二信号和读命令。 非易失性半导体存储器具有字线，存储单元阵列包括连接到字线的存储单元，以及接收第一信号，第二信号和读命令的第二接口部。

公开(公告)号：US09170935B2

公开(公告)日：2015-10-27

申请号：US13779603

申请日：2013-02-27

申请人： Kabushiki Kaisha Toshiba

发明人： Tomoyuki Kantani ,  Yoshii Akagawa

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F11/14 ,  G06F11/08 ,  G11C7/10 ,  G06F11/10 ,  G11C29/04

CPC分类号： G06F12/0246 ,  G06F11/08 ,  G06F11/1068 ,  G06F11/14 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7209 ,  G11C7/1006 ,  G11C2029/0411 ,  Y02D10/13

摘要： A semiconductor memory device includes a memory unit configured in page units, an error correction code (ECC) module for generating error correcting codes, a page information addition module for generating page information, and a controller for controlling the reading and writing of data to the memory unit. The controller is configured to associate error correction code information and page information with each frame unit of data written to the memory unit and to store the associated information with each frame unit. The controller is configured to output data to an external host in sizes less than one page unit, such as one frame unit.

摘要翻译： 半导体存储器件包括以页为单位配置的存储器单元，用于产生纠错码的纠错码（ECC）模块，用于产生页信息的页信息附加模块和用于控制数据读取和写入的控制器 存储单元 控制器被配置为将纠错码信息和页面信息与写入存储器单元的每个帧数据单元相关联并且存储与每个帧单元相关联的信息。 控制器被配置为以小于一页单位的尺寸（例如一个帧单位）向外部主机输出数据。