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公开(公告)号：US09129711B2
公开(公告)日：2015-09-08
申请号：US13919227
申请日：2013-06-17
发明人： Yasuhiko Kurosawa
CPC分类号： G11C29/021 , G11C16/00 , G11C29/028 , G11C29/42
摘要： According to one embodiment, a semiconductor memory device includes memory cells each given one of threshold voltages to store data, and a controller configured to use read voltages to determine threshold voltages of the memory cells. The controller is configured to use voltages over a window to read data from the memory cells to determine distribution of the threshold voltages of the memory cells to estimate a read voltage. The controller is further configured to execute the estimation of a read voltage for each of the read voltages. The controller is further configured to use an estimated value of a first read voltage of the read voltages to determine a window for estimation of a second read voltage of the read voltages.
摘要翻译： 根据一个实施例，半导体存储器件包括各自给出一个阈值电压以存储数据的存储单元，以及配置为使用读取电压来确定存储器单元的阈值电压的控制器。 控制器被配置为使用窗口上的电压来从存储器单元读取数据，以确定存储器单元的阈值电压的分布以估计读取电压。 控制器还被配置为执行每个读取电压的读取电压的估计。 控制器还被配置为使用读取电压的第一读取电压的估计值来确定用于估计读取电压的第二读取电压的窗口。
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2.发明申请MEMORY CONTROLLER, NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM 有权内存控制器，非易失性半导体存储器件和存储器系统公开(公告)号：US20160247561A1
公开(公告)日：2016-08-25
申请号：US14712017
申请日：2015-05-14
发明人： Masanobu SHIRAKAWA , Tsuyoshi Atsumi , Hidetaka Tsuji , Tomoyuki Kantani , Hideaki Yamamoto , Yasuhiko Kurosawa
IPC分类号： G11C11/56
CPC分类号： G11C11/5642 , G11C7/04
摘要： According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.
摘要翻译： 根据一个实施例，存储器系统包括非易失性半导体存储器和存储器控制器。 存储器控制器具有第一信号生成部，其生成与用于非易失性半导体存储器的读取操作的读取电压相关的第一信号;第二信号生成部，其生成指定用于温度校正的温度系数的第二信号 以及第一接口部分，其输出第一信号，第二信号和读命令。 非易失性半导体存储器具有字线，存储单元阵列包括连接到字线的存储单元，以及接收第一信号，第二信号和读命令的第二接口部。
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公开(公告)号：US09190159B2
公开(公告)日：2015-11-17
申请号：US13947493
申请日：2013-07-22
发明人： Yasuhiko Kurosawa
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/10 , G11C16/3404 , G11C16/349
摘要： Each memory cell has a threshold voltage to distinguish a storage data item. A controller generates one of storage data items from one or more sets of reception data, stores the storage data item, randomizes data transmission for memory cells, instructs the cells to store the randomized data, uses read voltage candidates to read storage data from the cells, counts a distribution of voltages stored in the cells for each read voltage candidate, specifies a minimum read voltage candidate where a sum of the counting exceeds an expected number, and uses the specified candidate as a read voltage to distinguish a first storage data item corresponding to the expected number and an adjacent second storage data item.
摘要翻译： 每个存储单元具有阈值电压以区分存储数据项。 控制器从一个或多个接收数据组中产生一个存储数据项，存储存储数据项，随机化存储单元的数据传输，指示单元存储随机数据，使用读电压候选从单元中读取存储数据 计算每个读取电压候选存储在单元格中的电压的分布，指定计数的和超过预期数的最小读取电压候选，并且使用指定的候选作为读取电压来区分对应的第一存储数据项 到预期数量和相邻的第二存储数据项。
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公开(公告)号：US09653156B2
公开(公告)日：2017-05-16
申请号：US14712017
申请日：2015-05-14
发明人： Masanobu Shirakawa , Tsuyoshi Atsumi , Hidetaka Tsuji , Tomoyuki Kantani , Hideaki Yamamoto , Yasuhiko Kurosawa
CPC分类号： G11C11/5642 , G11C7/04
摘要： According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.
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公开(公告)号：US09625986B2
公开(公告)日：2017-04-18
申请号：US14816402
申请日：2015-08-03
CPC分类号： G06F1/3296 , G06F1/3206 , G06F1/324 , Y02D10/126
摘要： According to one embodiment, a semiconductor device includes: an integrated circuit that has a plurality of power consumption modes different in power consumption; a temperature detection circuit that detects temperature of the integrated circuit; a counter that measures time taken for temperature change in the integrated circuit; and a state machine that causes a state transition to take place in the integrated circuit based on the temperature detected by the temperature detection circuit and the time measured by the counter, wherein the integrated circuit selects the power consumption mode based on the state subjected to transition by the state machine.
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公开(公告)号：US09081711B2
公开(公告)日：2015-07-14
申请号：US14090428
申请日：2013-11-26
发明人： Kenta Yasufuku , Shigeaki Iwasa , Yasuhiko Kurosawa , Hiroo Hayashi , Seiji Maeda , Mitsuo Saito
CPC分类号： G06F12/1063 , G06F12/0831 , G06F12/1027 , G06F12/1054 , G06F12/1081 , G06F12/12 , Y02D10/13
摘要： An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
摘要翻译： 实施例提供了一种虚拟地址高速缓存存储器，包括：TLB虚拟页面存储器，被配置为当对TLB的重写发生时，重写入口数据; 数据存储器，被配置为使用虚拟页标签或页偏移来保存高速缓存数据作为高速缓存索引; 高速缓存状态存储器，被配置为与高速缓存索引相关联地保存存储在数据存储器中的高速缓存数据的高速缓存状态; 第一物理地址存储器，被配置为当对所述TLB的重写发生时，重写所保持的物理地址; 以及第二物理地址存储器，被配置为当在发生对TLB的重写之后将高速缓存数据写入数据存储器时，重写保持的物理地址。
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公开(公告)号：US20140164702A1
公开(公告)日：2014-06-12
申请号：US14090428
申请日：2013-11-26
发明人： Kenta Yasufuku , Shigeaki Iwasa , Yasuhiko Kurosawa , Hiroo Hayashi , Seiji Maeda , Mitsuo Saito
CPC分类号： G06F12/1063 , G06F12/0831 , G06F12/1027 , G06F12/1054 , G06F12/1081 , G06F12/12 , Y02D10/13
摘要： An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
摘要翻译： 实施例提供了一种虚拟地址高速缓存存储器，包括：TLB虚拟页面存储器，被配置为当对TLB的重写发生时，重写入口数据; 数据存储器，被配置为使用虚拟页标签或页偏移来保存高速缓存数据作为高速缓存索引; 高速缓存状态存储器，被配置为与高速缓存索引相关联地保存存储在数据存储器中的高速缓存数据的高速缓存状态; 第一物理地址存储器，被配置为当对所述TLB的重写发生时，重写所保持的物理地址; 以及第二物理地址存储器，被配置为当在发生对TLB的重写之后将高速缓存数据写入数据存储器时，重写保持的物理地址。
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