公开(公告)号：US11239161B2

公开(公告)日：2022-02-01

申请号：US16808211

申请日：2020-03-03

Applicant: KIOXIA CORPORATION

Inventor： Yoichi Minemura

IPC: H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11514 ,  H01L27/11597 ,  H01L27/1157 ,  G11C16/26

Abstract: A memory device includes a semiconductor layer including adjacent cell and non-cell areas in a first direction, first and second conductive lines on the layer, extending along the first direction and arranged away from each other in a second direction crossing the first direction, conductor layers arranged above the semiconductor layer in a third direction crossing the first and second directions, pillars on the cell area, passing through the conductor layers in the third direction and forming memories at intersections with the conductor layers, and shunt lines extending along the second direction and arranged in the first direction above the cell area, each of the shunt lines connected to the first and second lines via third conductive lines. A length between the shunt line closest to the non-cell area and a boundary between the cell and non-cell areas is less than a length between adjacent shunt lines.

公开(公告)号：US11264105B2

公开(公告)日：2022-03-01

申请号：US16993509

申请日：2020-08-14

Applicant: Kioxia Corporation

Inventor： Kazuharu Yamabe ,  Yoichi Minemura

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, first and second word lines, and a bit line. The first and second memory cells are coupled to each other and adjacent to each other. When a state of the second memory cell is the first state or one of the states corresponding to a lower threshold voltage distribution than that of the first state, the first memory cell data is read in a first period during which a first voltage is applied to the second word line. And when the state of the second memory cell is the second state or one of the states corresponding to a higher threshold voltage distribution than the second state, the first memory cell data is read in a second period during which a second voltage higher than the first voltage is applied to the second word line.

公开(公告)号：US11563025B2

公开(公告)日：2023-01-24

申请号：US17004777

申请日：2020-08-27

Applicant: KIOXIA CORPORATION

Inventor： Yoichi Minemura ,  Kensei Takahashi ,  Takashi Asano

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/02 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor storage device includes first and second stacked bodies, a first semiconductor layer, a first charge storage layer, a conductive layer, and a first silicon oxide layer. The first stacked body includes first insulation layers and first gate electrode layers that are alternately stacked in a first direction. The first semiconductor layer extends in the first stacked body in the first direction. The first charge storage layer is provided between the first semiconductor layer and the first gate electrode layers. The conductive layer is provided between the first stacked body and the second stacked body and extends in the first direction and a second direction. The first silicon oxide layer is provided between the conductive layer and the first gate electrode layers. The first silicon oxide layer containing an impurity being at least one of phosphorus, boron, carbon, and fluorine.