公开(公告)号：US20230246015A1

公开(公告)日：2023-08-03

申请号：US18297849

申请日：2023-04-10

Applicant: KIOXIA CORPORATION

Inventor： Jun IIJIMA ,  Yumi NAKAJIMA

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/80894 ,  H01L2225/06524 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.

公开(公告)号：US20210091112A1

公开(公告)日：2021-03-25

申请号：US17010451

申请日：2020-09-02

Applicant: Kioxia Corporation

Inventor： Yumi NAKAJIMA ,  Satoshi NAGASHIMA

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/544

Abstract: According to one embodiment, a semiconductor device comprising: a first stacked structure in which first insulating layers and first conductive layers are alternately stacked; a second stacked structure in which second insulating layers and second conductive layers are alternately stacked; a first memory pillar provided in the first stacked structure; a first dividing structure dividing the first conductive layers; a second memory pillar provided within the second stacked structure and connected to the first memory pillar; a second dividing structure dividing the second conductive layers; a first alignment mark pillar provided in the first stacked structure and projecting from the first stacked structure; a second alignment mark pillar provided on the first alignment mark pillar; an alignment mark surrounded by the second alignment mark pillar.

公开(公告)号：US20210082946A1

公开(公告)日：2021-03-18

申请号：US16782697

申请日：2020-02-05

Applicant: KIOXIA CORPORATION

Inventor： Yumi NAKAJIMA

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556

Abstract: According to one embodiment, a semiconductor memory device includes a via provided above a substrate, a conductive layer provided on the via, and a via provided on the conductive layer. The via, the conductive layer, and the via are one continuous structure.

公开(公告)号：US20220199603A1

公开(公告)日：2022-06-23

申请号：US17692954

申请日：2022-03-11

Applicant: KIOXIA CORPORATION

Inventor： Jun IIJIMA ,  Yumi NAKAJIMA

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.