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公开(公告)号:US12034441B2
公开(公告)日:2024-07-09
申请号:US18165195
申请日:2023-02-06
Applicant: Kioxia Corporation
Inventor: Yasuhiro Hirashima , Masaru Koyanagi , Yutaka Takayama
IPC: G11C7/10 , H01L23/538 , H03K3/00 , H03K19/0175
CPC classification number: H03K19/017509 , H01L23/5384
Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.
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公开(公告)号:US11621712B2
公开(公告)日:2023-04-04
申请号:US17473012
申请日:2021-09-13
Applicant: KIOXIA CORPORATION
Inventor: Yasuhiro Hirashima , Masaru Koyanagi , Yutaka Takayama
IPC: G11C7/10 , H03K3/00 , H03K19/0175 , H01L23/538
Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.
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公开(公告)号:US11121710B2
公开(公告)日:2021-09-14
申请号:US17000708
申请日:2020-08-24
Applicant: KIOXIA CORPORATION
Inventor: Yasuhiro Hirashima , Masaru Koyanagi , Yutaka Takayama
IPC: G11C7/10 , H03K3/00 , H03K19/0175 , H01L23/538
Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.
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