公开(公告)号：US12020772B2

公开(公告)日：2024-06-25

申请号：US17716295

申请日：2022-04-08

Applicant: Kioxia Corporation

Inventor： Yasuhiro Hirashima ,  Mitsuhiro Abe ,  Norichika Asaoka

IPC: G11C7/10 ,  G11C29/12

CPC classification number: G11C7/1093 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C29/1201

Abstract: A semiconductor memory device includes: a first delay circuit configured to delay a first signal and provide a variable delay time; a first select circuit configured to select a second signal or a third signal based on the first signal delayed by the first delay circuit; a first circuit configured to output a fourth signal based on a signal selected and output by the first select circuit; a first output buffer configured to output a fifth signal based on the signal selected and output by the first select circuit; a first output pad configured to externally output the fifth signal; and a counter configured to count a number of times the fourth signal is output.

公开(公告)号：US12034441B2

公开(公告)日：2024-07-09

申请号：US18165195

申请日：2023-02-06

Applicant: Kioxia Corporation

Inventor： Yasuhiro Hirashima ,  Masaru Koyanagi ,  Yutaka Takayama

IPC: G11C7/10 ,  H01L23/538 ,  H03K3/00 ,  H03K19/0175

CPC classification number: H03K19/017509 ,  H01L23/5384

Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

公开(公告)号：US11218141B2

公开(公告)日：2022-01-04

申请号：US16723823

申请日：2019-12-20

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro Hirashima ,  Masaru Koyanagi

IPC: H03K5/01 ,  H03K5/156 ,  H03L7/099 ,  H03K5/26 ,  H03K5/06 ,  H03L7/07 ,  H03K7/08 ,  G06F1/06

Abstract: A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.

公开(公告)号：USRE49783E1

公开(公告)日：2024-01-02

申请号：US16654665

申请日：2019-10-16

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro Hirashima ,  Masaru Koyanagi

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/10

CPC classification number: G11C13/004 ,  G11C7/1084 ,  G11C7/109 ,  G11C13/0002

Abstract: A memory device includes a nonvolatile semiconductor memory cell array, a plurality of terminals through which control signals are received to control the memory device, an on-die termination circuit connected to at least one of the terminals and having a variable resistor, and a control circuit. The control circuit is configured to enable the on-die termination circuit in response to an enabling signal to enable the on-die termination circuit, with a resistance of the variable registor resistor at different values depending on whether a control signal is asserted or deasserted when the enabling signal is received.

公开(公告)号：US11450390B2

公开(公告)日：2022-09-20

申请号：US17118703

申请日：2020-12-11

Applicant: Kioxia Corporation

Inventor： Fumiya Watanabe ,  Masaru Koyanagi ,  Yutaka Shimizu ,  Yasuhiro Hirashima ,  Kei Shiraishi ,  Mikihiko Ito

IPC: G11C11/08 ,  G11C16/32 ,  G11C7/10 ,  G11C16/10

Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

公开(公告)号：US12298826B2

公开(公告)日：2025-05-13

申请号：US18181488

申请日：2023-03-09

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Yasuhiro Hirashima ,  Naoya Tokiwa

IPC: G06F1/28 ,  G11C16/04

Abstract: According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.

公开(公告)号：US12197732B2

公开(公告)日：2025-01-14

申请号：US17898370

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Kenta Shibasaki ,  Yoshihiko Shindo ,  Yasuhiro Hirashima ,  Akio Sugahara ,  Shigeki Nagasaka ,  Dai Nakamura ,  Yousuke Hagiwara

IPC: G06F3/06

Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

公开(公告)号：US12183405B2

公开(公告)日：2024-12-31

申请号：US17899014

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Mitsuhiro Abe ,  Yasuhiro Hirashima ,  Mitsuaki Honma

IPC: G11C16/32 ,  H01L25/065

Abstract: A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.

公开(公告)号：US11769535B2

公开(公告)日：2023-09-26

申请号：US17681592

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro Hirashima

IPC: G11C7/10 ,  G11C8/06

CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1057 ,  G11C8/06 ,  G11C2207/2254

Abstract: A semiconductor memory device includes a memory cell array, first and second pads, an interface circuit connected to the first pad and configured to transmit data input through the first pad to the memory cell array and output data received from the memory cell array through the first pad, a ZQ calibration circuit that is connected to the second pad and executes a ZQ calibration to generate a ZQ calibration value, and a sequencer configured to control the ZQ calibration circuit to apply the ZQ calibration value to the interface circuit. A command set is input through the first pad after reading data from the memory cell array to cause the interface circuit to output the data read from the memory cell array, and the ZQ calibration circuit executes the ZQ calibration after the command set is input and before the data is output through the first pad.

公开(公告)号：US11621712B2

公开(公告)日：2023-04-04

申请号：US17473012

申请日：2021-09-13

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro Hirashima ,  Masaru Koyanagi ,  Yutaka Takayama

IPC: G11C7/10 ,  H03K3/00 ,  H03K19/0175 ,  H01L23/538

Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.