公开(公告)号：US09658170B2

公开(公告)日：2017-05-23

申请号：US14308383

申请日：2014-06-18

Applicant: KLA-Tencor Corporation

Inventor： Guowu Zheng ,  Jehn-Huar Chern ,  Binu Balakrishnan Sathy

IPC: G01N21/95 ,  H04N5/372 ,  H04N5/378

CPC classification number: G01N21/9501 ,  H04N5/37206 ,  H04N5/378

Abstract: A Time Delay and Integration (TDI) imaging system utilizing variable voltage readout clock signals having progressively increasing amplitudes defined as a function of pixel row location, where pixel rows positioned to receive/collect/transfer image-related charges at the start of the TDI imaging process are controlled using lower amplitude readout clock signals than pixel rows positioned to receive/collect/transfer image-related charges near the end of the TDI process. The clock signal amplitude for each pixel row is determined by the expected maximum amplitude needed to hold and transfer image charges by the pixels of that row. Multiple (e.g., three) primary phase signals are generated that are passed through splitters to provide multiple identical secondary phase signals, and then drivers having gain control circuitry are utilized to produce voltage readout clock signals having the same phases as the primary phase signals, but having two or more different voltage amplitudes.

公开(公告)号：US20150002655A1

公开(公告)日：2015-01-01

申请号：US14308383

申请日：2014-06-18

Applicant: KLA-Tencor Corporation

Inventor： Guowu Zheng ,  Jehn-Huar Chern ,  Binu Balakrishnan Sathy

IPC: G01N21/95 ,  H04N5/378 ,  H04N5/372

CPC classification number: G01N21/9501 ,  H04N5/37206 ,  H04N5/378

Abstract: A Time Delay and Integration (TDI) imaging system utilizing variable voltage readout clock signals having progressively increasing amplitudes defined as a function of pixel row location, where pixel rows positioned to receive/collect/transfer image-related charges at the start of the TDI imaging process are controlled using lower amplitude readout clock signals than pixel rows positioned to receive/collect/transfer image-related charges near the end of the TDI process. The clock signal amplitude for each pixel row is determined by the expected maximum amplitude needed to hold and transfer image charges by the pixels of that row. Multiple (e.g., three) primary phase signals are generated that are passed through splitters to provide multiple identical secondary phase signals, and then drivers having gain control circuitry are utilized to produce voltage readout clock signals having the same phases as the primary phase signals, but having two or more different voltage amplitudes.

Abstract translation: 时间延迟和积分（TDI）成像系统利用具有逐渐增加的幅度的可变电压读出时钟信号，该幅度被定义为像素行位置的函数，其中像素行被定位为在TDI成像开始时接收/传送图像相关电荷 使用较低幅度读出时钟信号控制处理，该像素行位于与TDI处理结束附近接收/传送/传送图像相关电荷的像素行。 每个像素行的时钟信号幅度由通过该行的像素保持和传送图像电荷所需的预期最大幅度确定。 产生多个（例如三个）主相位信号，其通过分离器传递以提供多个相同的次级相位信号，然后利用具有增益控制电路的驱动器产生具有与主相位信号相同相位的电压读出时钟信号，但是 具有两个或更多个不同的电压幅度。